Data transferring system

TL;DR: In this paper, the authors propose to improve the efficiency of data transfer by discriminating interlock transfer or split one with a requesting device according to the response of the opposite device at the time of requesting input in input transfer.

Abstract: PURPOSE:To improve the efficiency of data transfer by discriminating interlock transfer or split one with a requesting device according to the response of the opposite device at the time of requesting input in input transfer. CONSTITUTION:Response status signals BSSTSA-00, and BSSTSB-00 from the opposite device that has received a request for data transfer are decoded by a decoder 13, and in the case of split transfer, a signal BSSACK+10 goes to a logic value 1. In case of the interlock transfer, a signal BSIAK+10 goes to the logic value 1. The signal BSSACK+10 is inputted to an NAND gate 20, after reversed, goes to MYBSYR-00 through an AND gate 14 and resets an FF9. Therefore, the signal MYBUSY+00 annihilates and bus occupation display signal BSBUSY-00, returns to a logic value 0, which releases occupation of the bus. On the other hand, the signal BSIACK+00 is inputted to an FF22, and sets a signal INTLOK+00, and the signal BSBUSY-00 holds the logic 1 which continues to occupy th bus.