Data transfer control system

TL;DR: In this article, a memory access control part 22b detects a request for transfer of blocks by a DMA mode signal and switches the lower two bits of a receiver 23 to the side of an address counter 25.

Abstract: PURPOSE:To transfer the block data at a high speed by producing plural reading addresses through a memory in response to a reading start address when a mode signal indicates the transfer of block and then outputting the plural corresponding data from a memory element. CONSTITUTION:A memory access control part 22b detects a request for transfer of blocks by a DMA mode signal and switches the lower two bits of a receiver 23 to the side of an address counter 25. A memory element 20 receives the start address of an A-BUS and the addresses of the lower two bits from an address counter 25 via the receiver 23 and performs access. At the same time, a memory control part 22 produces an answer signal SRVO through the part 22b and delivers it to an answer signal line C1. Then a memory 2 counts up a counter 22a which counts the output frequencies of the answer signal to 21 strobes and the counter 25 to give an access to the next word of the memory element 20. Then the part 22b stops the access of the element 20 when the count value of the counter 22a reaches '4' to deliver data four times, i.e., to transmit answer signals four times.