Data transfer apparatus

TL;DR: In this paper, a 9-bit address identifying an output line is provided with each message on an associated address line, and the 64 data bits of each message received during a 64-bit message input period are stored in a memory array.

Abstract: Apparatus for transferring messages received at any of four inputs to any of 512 outputs. Messages of 64 bits each may be present on any of four data input lines simultaneously. A 9-bit address identifying an output line is provided with each message on an associated address line. The 64 data bits of each message received during a 64-bit message input period are stored in a memory array. The four most significant bits (MSB) of each address are stored in one memory array and the five least significant bits (LSB) of each address are stored in another memory array. During the next 64-bit period the five LSB''s of the stored addresses are compared with the count of a 5-bit (32 count) counter. When a comparison occurs, the appropriate four MSB''s of the address are read out of the memory array and the 64 data bits are also read out of the memory. The four MSB''s of the address are decoded to select the proper one of sixteen groups of of 32 output lines to which the data is to be directed. The 64 bits of data are received in parallel and accepted by the proper output group. Under control of the 5-bit counter, the output group converts the data from parallel to serial form and demultiplexes the serial data to direct it to the proper one of the 32 output lines of the group. The apparatus includes a second set of data and address memories so that a second set of messages can be received and stored while the information in the first set is being read out.