Patent
Data storage systems
Frederick H. Rees,Dan Bleicher +1 more
- 13 Nov 1978
2
TL;DR: In this article, the queueing of interexchange messages in a multi-exchange digital telecommunication network is provided using a dynamic store into cells of which the messages are placed.
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Abstract: Queuing of interexchange messages in a multi-exchange digital telecommunication network is provided using a dynamic store into cells of which the messages are placed. A subsidiary control store has a cell for each cell of the message store and each of these cells contains a control word which contains the status-busy/free of its message cell, plus details of the message including the user for which it is stored when the cell is busy. These details include message priorities, so that queues of messages awaiting attention can be assembled in the store.
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Citations
Patent
Method and apparatus for displaying textual or graphic data on the screen of television receivers
Daniel S. Kwoh
- 13 Nov 1996
TL;DR: In this article, a local language is pre-stored in permanent memory and equivalent data is transmitted in the vertical blanking interval (VBI) to television receivers for future display.
124
Patent
A queue managing method for an electronic mail system
Richard E. Batchelor
- 17 Dec 1991
TL;DR: A queue manager for controlling the execution of requests for the transport of messages from users to destinations is proposed in this paper, which includes a queue for storing pending requests and a dispatcher task for creating a worker task to execute each request.
17
References
Patent
System for transferring data
F Sherman
- 29 Dec 1972
TL;DR: In this paper, a 9-bit address identifying an output line is provided with each message on an associated address line, and the 64 data bits of each message received during a 64-bit message input period are stored in a memory array.
8
Patent
Intermediate exchange for telecommunication
Dahlblom Rolf August,Edstroem Nils Herbert,Jan Silwer +2 more
- 26 Jul 1966
8
Patent
Data transfer apparatus
F Sherman
- 29 Dec 1972
TL;DR: In this paper, a 9-bit address identifying an output line is provided with each message on an associated address line, and the 64 data bits of each message received during a 64-bit message input period are stored in a memory array.
4
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