Patent
Data processing system with memory-access priority control
Hidehiko Nishida
- 21 Nov 1991
9
TL;DR: In this article, a data processing system including a plurality of multi-processor systems, each multi-processor system having at least one central processing unit and one main memory both connected to a memory control unit is detected, and the registers to store the access request signals in the other multiprocessor system are efficiently used by adding a priority control signal to the access requests signal.
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Abstract: In a data processing system including a plurality of multi-processor systems, each multi-processor system having at least one central processing unit and at least one main memory both connected to a memory control unit, each memory control unit is connected to each other memory control unit, the memory control unit comprises plural ports, plural registers, access selection circuits for innner and outer access, a priority control circuit, a first and a second control circuit, and wait signal reset circuit, a priority of accesses from the same central processing unit to the other multi-processor system is detected, and the registers to store the access request signals in the other multi-processor system are efficiently used by adding a priority control signal to the access request signal. Thus, the data throughput of the system and the speed of the access are improved.
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Citations
Patent
Cache coherent network adapter for scalable shared memory processing systems
Howard Thomas Olnowich
- 10 Jul 1997
TL;DR: In this paper, a shared memory parallel processing system interconnected by a multi-stage network combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently.
96
Patent
Multi-processor data processing system with control for granting multiple storage locks in parallel and parallel lock priority and second level cache priority queues
Kelvin S. Vartti,Mitchell A. Bauman +1 more
- 28 Dec 1995
TL;DR: In this article, a storage lock apparatus for a multiprocessor data processing system is described, which includes control for granting locks to different selectable portions of storage in parallel.
93
Patent
Memory queue with adjustable priority and conflict detection
Mitchell A. Bauman,Jerome G. Carlin,Roger L. Gilbertson +2 more
- 15 Mar 1995
TL;DR: In this article, an improved memory request storage and allocation system using parallel queues to retain different categories of memory requests until they can be acted on by the main memory is presented, where the queue priority scheme is based on an adjustable ratio, which determines the rate at which memory requests from one queue are allowed to access the main main memory versus memory request from other queues.
39
Patent
Data processing system having subsystems connected by busses
Takeshi Aimoto,Akira Ishiyama,Hidenori Kosugi,Shibata Masabumi +3 more
- 20 Mar 1992
TL;DR: In this paper, a data processing system is provided which includes a plurality of subsystems each including at least one instruction processor, an input/output device and a main storage device connected by local bus.
18
Patent
Data processing apparatus security
Rahoul Kumar Varma,Marc Richard Wicks,Gareth Duncan,David Francis McHale,Mike Livesley +4 more
- 15 Feb 2005
TL;DR: In this article, a cache interface logic is proposed to determine whether a non-secure data access request is associated with a region of secure data values by interrogating a data region allocation table.
13
References
Patent
Data processor system having improved data throughput in a multiprocessor system
Hidehiko Nishida
- 17 Dec 1984
TL;DR: In this paper, a data processor system includes a plurality of multiprocessor systems, which are connected through each memory control unit of each multi-processor system by interface lines.
24
Patent
Priority assignment apparatus for use in a memory controller
Marvin K. Webster
- 27 Mar 1978
TL;DR: In this article, an apparatus for assigning priority to information temporarily stored in memory controller stack is described. But it does not specify a hierarchy of comparators and associated control logic to determine the stack level which contains information which has been stored the longest.
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