Patent
Data processing system having a cache and method therefor
William C. Moyer,John Arends,Lea Hwang Lee +2 more
- 14 Nov 1996
41
TL;DR: In this paper, a look ahead feature for the valid bit array is provided, such that during a read of the cache, the valid bits for a next instruction is checked with the same index used to read the current instruction, so that the program can remain active as long as the program is in a loop which can be contained entirely within the cache.
read more
Abstract: A data processing system (20) has a cache (26) that does not use a TAG array for storing a TAG address as in a conventional cache. The cache (26), according to one embodiment, uses a state machine (30) for transitioning the cache (26) to an active state in response to a change of flow instruction which is a short backward branch instruction of a predetermined displacement. The predetermined displacement is less than the number of entries in the cache (26), so the cache can remain active as long as the program is in a loop which can be contained entirely within the cache. A look ahead feature for the valid bit array is provided that associates the valid bit for a current instruction with a previous instruction, such that during a read of the cache, the valid bit for a next instruction is checked with the same index used to read the current instruction.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Patent
Loop cache memory and cache controller for pipelined microprocessors
Richard H. Scales
- 14 May 2001
TL;DR: In this paper, a microprocessor with a loop cache controller is described, which is connected in communication with the instruction pipeline, such that it may both store instructions from the instruction pipelines and issue instructions to be executed by the execution units.
48
Patent
Method and apparatus for loop buffering digital signal processing instructions
Ganapathy Kumar,Kanapathipiillai Ruban,Kenneth Malich +2 more
- 25 Jan 2001
TL;DR: In this paper, a loop buffer for storing and holding instructions executed within loops for digital signal processing is proposed, where the loop buffer conserves power by avoiding the fetching of instructions unnecessarily from memory.
45
Patent
Pin management of accelerator for interpretive environments
Phillip M. Adams
- 24 May 1999
TL;DR: In this article, an instruction set implementing a virtual machine may store each instruction in a single cache line as a compiled, linked loaded image, and after loading, the cache is pinned, disabled from flushing the contents or replacing the contents of any cache line.
36
Patent
Reverse NFA Generation And Processing
Rajan Goyal,Satyanarayana Lakshmipathi Billa +1 more
- 24 Sep 2015
TL;DR: In this paper, a reverse non-deterministic finite automata (rNFA) graph is generated for a specific type of the at least one given pattern by walking the input sequence of characters backwards through the rNFA beginning from an offset of the input sequences of characters associated with the marked node.
35
Low-Cost Embedded Program Loop Caching - Revisited
Lea Hwang Lee,Bill Moyer,John H. Arends +2 more
- 01 Jan 1999
TL;DR: The modified loop caching scheme proposed in this paper is capable of capturing only part of the program loop without having any cache conflict problem, and can reduce instruction fetch energy more than other loop cache schemes previously proposed.
References
Power consumption estimation in CMOS VLSI chips
Dake Liu,Christer Svensson +1 more
TL;DR: In this article, power consumption of logic circuits, interconnections, clock distribution, on chip memories, and off chip driving in CMOS VLSI has been estimated and an estimate tool is created.
476
Cache design trade-offs for power and performance optimization: a case study
Ching-Long Su,Alvin M. Despain +1 more
- 23 Apr 1995
TL;DR: This paper examines performance and power trade-offs in cache designs and the effectiveness of energy reduction for several novel cache design techniques targeted for low power.
Decoupled sectored caches: conciliating low tag implementation cost and low miss ratio
A. Seznec
- 18 Apr 1994
TL;DR: A decoupled sectored cache will allow the same level of performance as a non-sectored cache, but at a significantly lower hardware cost.
126
Reducing the frequency of tag compares for low power I-cache design
Ramesh Panwar,David Rennels +1 more
- 23 Apr 1995
TL;DR: Three architectural modi cations are presented, which in concert, allow us to reduce the cache controller activity to less than 2% for most applications.
Cache designs for energy efficiency
Ching-Long Su,A.M. Despain +1 more
- 04 Jan 1995
TL;DR: Experimental results suggest that both the block buffering and Gray code addressing techniques are ideal for instruction cache designs which tend to be accessed in a consecutive sequence and can achieve an order of magnitude energy reduction on caches.
87