Patent
Data error detection and correction system
William J. Walker,Alan L. Goodrum,Dale J. Mayer +2 more
- 14 Oct 1994
42
TL;DR: In this article, a system that performs error correction and detection of data read from memory in a computer system having a processor bus and a system bus is presented, where a pair of data buffers are used to interface between the memory and the processor data bus or the system data bus.
read more
Abstract: A system that performs error correction and detection of data read from memory in a computer system having a processor bus and a system bus. A pair of data buffers are used to interface between the memory and the processor data bus or the system data bus. Each data buffer receives half the data bits from the memory array, from the processor data bus, and from the system data bus. Each of the data buffers contains logic for performing error detection and correction. To enable error correction, check bits are generated by the data buffers in a write cycle to the memory. A feature of the present invention is that half the check bits are provided to one data buffer and the second half is provided to other data buffer. When a memory read cycle is performed, the retrieved check bits and data bits are examined according to the error correction algorithm to determine if a single bit correctable error has occurred. If so, the erroneous data bit is flipped. If a multiple bit error is detected, the microprocessor is interrupted to take appropriate remedial actions.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Patent
Semiconductor memory device.
Tomoharu Tanaka,Hiroshi Nakamura,Toru Tanzawa +2 more
- 12 Mar 2008
TL;DR: In this paper, the read circuit senses a change in a voltage of the bitline of a bitline, and applies a voltage which is different from the first voltage to the gate of the first transistor when it senses a voltage change.
119
Patent
Error detection and correction
Sompong P. Olarig,Michael F. Angelo +1 more
- 19 Dec 1996
TL;DR: In this article, the error detection and correction device generates a syndrome table which includes a plurality of entries mapped to correctable or uncorrectable errors, in which a detected multiple-bit error in the memory data bits is mapped to an incorrect error entry and a detected error in memory address bits are mapped to a incorrect error.
110
Patent
32-bit mode for a 64-bit ECC capable memory subsystem
Kenneth C. Creta,Elliot Garbus +1 more
- 29 May 1998
TL;DR: In 32-bit mode, each data block will have an 8-bit ECC value, which is consistent with ECC values generated for 64-bit data as discussed by the authors, which allows a memory subsystem to be optimized for bandwidth and latency depending upon this application.
87
Patent
Method for performing a command cancel function in a dram
Wayne F. Ellis,Mark W. Kellogg,Daniel J. Phipps +2 more
- 01 Apr 2003
TL;DR: In this paper, the authors propose a method for performing a common cancel (CC) function on a dynamic random access memory (DRAM) device to improve reliability and speed of a memory system.
63
Patent
System and method for more efficiently using error correction codes to facilitate memory device testing
Partha Gajapathy,Todd A. Dauenbaugh +1 more
- 23 May 2006
TL;DR: In this paper, a memory device includes an ECC and test circuit, and the test data bits are applied to the ECC encoder that is used in normal operation, which is designed so that it generates ECC bits that have the same logic level as the tested data bits.
36
References
Patent
Semiconductor memory device
Maeno Hideshi
- 20 Jul 1989
TL;DR: In this article, the authors proposed a solution to obtain a semiconductor memory device having improved integration by having a gate connected to a read word line RWLn, and a source connected to read bit line RBLn.
53
Patent
Error detecting method and apparatus for computer memory having multi-bit output memory circuits
James A Jackson,Kevin M Lowderman,Marc A Quattromani +2 more
- 29 Jan 1991
TL;DR: In this paper, an error correcting code and apparatus are used in conjunction with a main memory in which a data word is stored in a plurality of circuits each of which produces multiple outputs.
40
Patent
Semiconductor memory having error correction circuit
Masashi Horiguchi,Masakazu Aoki,Kiyoo Itoh +2 more
- 12 Jan 1989
TL;DR: In this paper, the authors proposed a semiconductor memory which comprises a plurality of memory blocks for storing information bits, another memory block for storing test bits, and a multiplicity of error correction circuits (e.g., parity test circuits), each responding to bit information for a parity test which is generated from one output from the corresponding one of the multiplexers (26), and a syndrome bus (22) responding to both the respective outputs of the parity test circuit (26) and the output of the other memory block (13).
39
Patent
Error detection and correction coding
W. Daniel Hillis
- 07 Sep 1988
TL;DR: In this article, a method of detecting bit errors in a possibly corrupted version of an original data word, the bits of the original data words (e.g., a 32-bit data word) being organized in nibbles of four bits each, each nibble being stored in a single four-bit memory chip.
35
Patent
ECC circuit failure detector/quick word verifier
Aichelmann Frederick John
- 27 Oct 1986
TL;DR: In this paper, a circuit for quickly determining if all of the data bits in an ECC word are correct and/or for detecting failures in an error detection syndrome generation path is presented.
31