Patent
Data correction circuit
Deepak K. Singh
- 24 Aug 2007
4
TL;DR: In this paper, a circuit and method for correcting binary values in a data word having N bit positions where the circuit includes several assemblies, each for a unique data word bit position, where each assembly includes a first logic circuit connected to its unique data-word bid and an adjacent dataword bit to provide a first output bit and a second logic circuit connecting to receive the first output bits and a different adjacent bit of the data word to provide the second output bit representing a corrected value of the unique bit.
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Abstract: A circuit and method are provided for correcting binary values in a data word having N bit positions where the circuit includes several assemblies, each for a unique data word bit position, where each assembly includes a first logic circuit connected to its unique data word bid and an adjacent data word bit to provide a first output bit and a second logic circuit connected to receive the first output bit and a different adjacent bit of the data word to provide a second output bit representing a corrected value of the unique bit.
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Citations
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Error recovery within integrated circuit
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- 24 Aug 2007
TL;DR: In this paper, a method and circuit for measuring frequency response performance of an integrated circuit by providing a pulse having a rising edge and a falling edge where the pulse is provided to a plurality of serially connected components.
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Application scheduling in heterogeneous multiprocessor computing platform based on a ratio of predicted performance of processor cores
Ravishankar Iyer,Sadagopan Srinivasan,Li Zhao,Ramesh Illikkal +3 more
- 25 Sep 2010
TL;DR: In this paper, the authors describe methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms. But they do not discuss the application scheduling in the context of heterogeneous multi-core systems.
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