Patent
Data conversion device and data conversion method
Tetsuya c,o Mitsubishi Electr. E. Co. Ichikawa,Tomomi c,o Mitsubishi Denki K. K. Kasuya,Mitsuru c,o Mitsubishi Denki K. K. Matsui +5 more
- 07 Mar 2003
44
TL;DR: In this paper, a sub-converter is provided in a data conversion apparatus for data encryption/decryption, where the sub converter converts data and transfers data that is nonlinear converted in a main converter or a key that is outputted from a key KL register 240 by switching between the data conversion function and data or key transfer function.
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Abstract: A sub converter 330 provided in a data conversion apparatus for data encryption/decryption includes a data conversion function and a data transfer function or key transfer function, the sub converter converts data and transfers data that is nonlinear converted in a main converter 320 or a key that is outputted from a key KL register 240, by switching between the data conversion function and the data or key transfer function.
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Citations
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Encryption processing device, encryption processing method, and program
Kyoji Shibutani,Atsushi Mitsuda,Toru Akishita,Takanori Isobe,Taizo Shirai,Harunaga Hiwatari +5 more
- 20 Feb 2012
TL;DR: An encryption processing device including an encryption processing part configured to divide configuration bits of data to be data processed into plural lines and to input, and to repeatedly execute data conversion processing applying a round function to each line of data as a round calculation as discussed by the authors.
24
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Encryption processing apparatus, encryption method, and computer program
Taizo Shirai,Kyoji Shibutani,Toru Akishita,Shiho Moriai +3 more
- 29 Aug 2007
TL;DR: In this paper, a common-key blockcipher processing structure that makes analysis of key more difficult and enhances security and implementation efficiency is realized, where a secret key is input to an encryption function including a round function employed in an encryption processing part to generate an intermediate key.
24
References
A Compact Rijndael Hardware Architecture with S-Box Optimization
Akashi Satoh,Sumio Morioka,Kohji Takano,Seiji Munetoh +3 more
- 09 Dec 2001
TL;DR: Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described, including a new composite field and the S-Box structure is also optimized.
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