Cpu logical simulation system

TL;DR: In this article, an instruction generating state asynchronous with the execution of an instruction string without interfering the operation of a CPU logic file and to attain simulation similar to real CPU operation is presented.

Abstract: PURPOSE:To prepare an instruction generating state asynchronous with the execution of an instruction string without interfering the operation of a CPU logic file and to attain simulation similar to real CPU operation. CONSTITUTION:In addition to a CPU defining instruction group 101, an exclusive instruction group 102 for starting an external or fault interruption is prepared. An automatic test program generating part 103 selects an instruction from the groups 101, 102 like a random number to prepare a test program 104. In the case of an exclusive instruction, an exclusive library group 109 is referred to and an exclusive instruction corresponding to a CPU to be simulated is substituted for the instruction concerned. A logical simulator 105 inputs the test program 104, and when the program 104 is a CPU defining instruction, transfers the instruction to an instruction fetching part in a CPU logical file 106 as it is. When the program 104 is an exclusive instruction the simulator 105 starts a false procedure 107 corresponding to the sort of an interruption and applies the interruption to the file 106.