Journal Article10.1145/383251.383255
Constrained polygon transformations for incremental floorplanning
TL;DR: It is shown that the constrained polygon transformation problem is NP-hard and several fast algorithms that produce results within a few percent of a theoretical lower bound on several floorplans are presented.
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Abstract: A productivity-driven methodology for incremental floorplanning is described and the constrained polygon transformation problem, a key step of this methodology, is formulated. The input to the problem consists of a floorplan computed using area estimates and the actual area required for each subcircuit of the floorplan. Informally, the objective is to change the areas of the modules without drastically changing their shapes or locations. We show that the constrained polygon transformation problem is NP-hard and present several fast algorithms that produce results within a few percent of a theoretical lower bound on several floorplans.
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Citations
A novel thermal optimization flow using incremental floorplanning for 3D ICs
Xin Li,Yuchun Ma,Xianlong Hong +2 more
- 19 Jan 2009
TL;DR: Experimental results show that migrating computation, growing unit and moving hotspot can reduce max on-chip temperature by 7%, 13% and 15% respectively on MCNC/GSRC benchmarks, and experimental results also show that the thermal optimization flow can achieve better area and total wirelength improvement than individual operations do.
34
Full Length Article: 3D thermal-aware floorplanner using a MILP approximation
TL;DR: A novel multi-objective formulation to consider the thermal and performance constraints in the optimization approach, an efficient Mixed Integer Linear Programming representation of the floorplanning model, and a smooth integration of the MILP model with an accurate thermal modelling of the architecture are proposed.
28
3D thermal-aware floorplanner using a MOEA approximation
TL;DR: This work proposes a novel 3D thermal-aware floorplanner for many-core single-chip architectures and shows promising improvements of the mean and peak temperature, as well as the thermal gradient, with a reduced overhead in the wire length of the system.
21
Constrained floorplanning using network flows
Yan Feng,Dinesh P. Mehta,H. Yang +2 more
TL;DR: Algorithms for a constrained version of the "modern" floorplanning problem proposed by Kahng in "Classical Floorplanning Harmful?" are presented and CMFP is shown to be negative-positive hard.
14
References
VLSI module placement based on rectangle-packing by the sequence-pair
TL;DR: This paper attacks the biggest MCNC benchmark ami49 with a conventional wiring area estimation method, and obtain a highly promising placement, and proposes a solution space where each packing is represented by a pair of module name sequences, called a sequence-pair.
748
Module packing based on the BSG-structure and IC layout applications
TL;DR: A new method of packing the rectangles is proposed with applications to integrated circuit (IC) layout design, called the bounded-sliceline grid, which consists of special segments that dissect the plane into rooms to which binary relations "right-of" and "above" are associated.
150
•Proceedings Article
Proceedings of the 2009 International Conference on Computer-Aided Design
Jaijeet Roychowdhury
- 02 Nov 2009
TL;DR: The ICCAD program this year includes three special sessions, as well as two designer sessions, all focused on providing additional broad perspectives for the authors' CAD audience, and continuing a practice started last year, ICCAD will integrate its tutorials within the technical program Monday through Wednesday.
122
Floor-planning by graph dualization: 2-concave rectilinear modules
Kok-Hoo Yeap,Majid Sarrafzadeh +1 more
TL;DR: It is shown that if only zero-concave rectilinear modules (CRM) and 1-CRM are allowed, there are PTGs that do not admit any floor-plan, but if 2-bend modules (e.g., T-shaped and Z-shaped) are also allowed, then every biconnected PTG admits afloor-plan.
92
Floorplan design of VLSI circuits
D. F. Wong,C. L. Liu +1 more
TL;DR: This paper presents two algorithms for the floorplan design problem that use Polish expressions to represent floorplans and employ the search method of simulated annealing.
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