Patent
Concurrent task and instruction processor and method
Maxwell C. Gilliland,Burton J. Smith,Gary L. Ferguson +2 more
- 16 Oct 1978
116
TL;DR: In this paper, a processor for concurrent processing of tasks and instructions is described, which is basically a multiple instruction, multiple data stream (MIMD) digital computer that utilizes pipelining for control and function units but avoids precedence constraint penalties.
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Abstract: A processor and method for concurrent processing of tasks and instructions are disclosed. The processor is basically a multiple instruction, multiple data stream (MIMD) digital computer that utilizes pipelining for control and function units, but avoids precedence constraint penalties. Task and instruction processing is carried on concurrently through the use of a snapshot taken of the next process status words (PSWs) to be serviced for each active task, the pointers for which are stored in task first in-first out buffers (task FIFOs). The PSWs, along with their parent task status words (TSWs), are placed into the control pipeline one at a time and serviced, after which each PSW pointer is placed back in the task FIFO from where it was taken. After all process status words of the snapshot have been entered into the control pipeline, a new snapshot is taken and the PSWs processed in the same manner. Instruction execution is carried out as the TSW/PSW pair proceeds through the control pipeline, during which time the required data operations are carried out by pulling operands from a memory unit, as required for execution of that particular instruction, and causing the same to be sent to the function units after which the results are placed in the memory unit. For interprocess data transfers, synchronization is accomplished through use of hardware implemented semaphores called a scoreboard. In addition, passage of data between processors and memories other than those associated, or local, memories, is through a memory switch.
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Citations
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244
References
Patent
Pipelined high speed arithmetic unit
Stephenson C,Watson W +1 more
- 28 Apr 1972
TL;DR: In this paper, a digital computer central processing unit is disclosed having an arithmetic unit which forms an element of an instruction processing pipeline, and the arithmetic unit has within it a plurality of arithmetic subunits each with its own storage and partitioned on a functional basis for the simultaneous execution of a pluralityof arithmetic steps within the arithmetic units while a plurality-of- instructions are simultaneously processed in their flow to the assembly.
74
Patent
Instruction selection in a two-program counter instruction unit
Fennel Jun John Wenard
- 31 Aug 1971
TL;DR: In this paper, an instruction handling unit specifically designed for pipeline processing of instructions is disclosed, and an apparatus is employed for sharing the instruction unit processing capabilities among two programs, which performs certain checks upon the specific instructions of the two different instruction streams and determines from various machine conditions and variable program conditions which instruction will be executed within the instruction processing unit.
27