Patent
Computer graphics system having high performance multiple layer Z-buffer
Stephanie Winner,Michael W. Kelley +1 more
- 06 May 1994
60
TL;DR: In this paper, the authors describe a computer graphics system having a processor for generating objects for display, a multi-layered Z-buffer for storing data according to their relative depths, the processor also compositing the data stored in the Zbuffer, a frame buffer for storing composited data, and two registers for facilitating the Z-buffering process.
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Abstract: A computer graphics system having a processor for generating objects for display, a multi-layered Z-buffer for storing data according to their relative depths, the processor also compositing the data stored in the Z-buffer, a frame buffer for storing composited data, a display for displaying an image as a number of pixels responsive to the composited data in the frame buffer, and two registers for facilitating the Z-buffering process is disclosed. One of the registers stores a number indicating how many of the layers in the Z-buffer contain visible data dependent on opacity of existing objects. In the other register, a number of addresses corresponding to each of the layers of the Z-buffer are stored. Each address specifies a location where data of one of the layers is stored. A determination is made as to which layer data associated with an incoming object is to be inserted. This determination depends on the contents of the first register as well as the value of the incoming object relative to those of objects already stored in the Z-buffer. The addresses of the second register are arranged to correspond to the appropriate layers in response to insertion of the incoming data.
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Citations
Patent
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Alan Heirich,Laurent Moll,M. Shand,Albert Tam,Robert W. Horst +4 more
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TL;DR: In this paper, an image generator is organized into a plurality of rendering engines, each of which renders an image of a part scene and provides the part image to a merge engine associated with that rendering engine.
163
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Patent
System and method for accelerated occlusion culling
Daniel M. Olsen,Noel D. Scott,Robert J Casey +2 more
- 26 Jul 1996
TL;DR: An occlusion culling circuit for use in a graphics computer receives graphics primitives data including x and y coordinates for each pixel, a z depth value, and r, g, b, and a or index color data as discussed by the authors.
86
Patent
System and method for merging pixel fragments based on depth range values
Kurt B C O Silicon Grap Akeley,Carroll Philip c +1 more
- 21 Nov 1996
TL;DR: In this article, a system and method for merging received pixel fragments with an existing fragment compares a depth range for the received fragment with a depth ranges for the existing fragment, if there is a range overlap, the new fragment is merged with the existing pixel fragment for which there is overlap.
81
Patent
Deferred scanline conversion architecture
Matthew James Patrick Regan
- 18 Jun 1999
TL;DR: The deferred scanline converter as mentioned in this paper uses a front-end processor to identify the triangles that are in competition for a given pixel location, and determines the winning triangle from among the competing triangles to generate the pixel for that pixel location.
78
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Michael F. Deering,Stephanie Winner,Bic Schediwy,Chris Duffy,Neil Hunt +4 more
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Transparency and antialiasing algorithms implemented with the virtual pixel maps technique
TL;DR: A system implementation is presented to illustrate the types of hardware rendering algorithms that benefit from the concept of virtual pixel maps, and two specific algorithms are used as examples.
237