Patent
Computer-based system and method for debugging a computer system implementation
Gregory D. Burroughs,Eric Delano,Steven W. LaMar +2 more
- 01 Jul 1992
39
TL;DR: Synchronization of an architectural model of a computer architecture and a behavioral model of an implementation of the architecture for functional verification of the implementation is discussed in this article, where a communication channel is established between the two models through which simulation control and state information can be communicated and both models are available for simulating.
read more
Abstract: Synchronization of an architectural model of a computer architecture and a behavioral model of an implementation of the architecture for functional verification of the implementation. A communication channel is established between the two models through which simulation control and state information can be communicated and both models are available for simulating. Synchronization points in the models' executions are identified, and a synchronizer is implemented which instructs each model to simulate to a synchronization point and report relevant state information. The synchronizer can also verify state information from the two models in real time, flag errors, or instruct the architectural model to modify its state either to match known errors in the behavioral model or to match correct behavior to an asynchronous event.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Patent
Apparatus and methods for real-time multimedia network traffic management and control in wireless networks
Augustine Samba
- 10 Jun 2010
TL;DR: In this article, the authors proposed a real-time network management procedure for multimedia streaming traffic in wireless networks and clusters of independent networks respectively, which is based on the Heterogeneous Service Creation (HSE) system.
106
Patent
Verification support system
Naoki Sano,Takeshi Yamamoto,Manabu Noriyasu,Satoru Natsui,Yuji Amano,Atsushi Ogasawara,Yuko Mizuta,Yoko Takihana +7 more
- 11 Apr 1995
TL;DR: In this paper, a verification support system has been proposed for the verification of a program using logic simulation, where the execution and verification of the steps up to one step before the error point is omitted and execution and validation are performed immediately from the error points, for the purpose of error correction.
74
Patent
System simulation for testing integrated circuit models
Vilas V. Gupte,Sanjay Adkar +1 more
- 18 Jul 1996
TL;DR: In this article, the ASIC design is verified utilizing information from a system simulation in the customer's system environment, and the test bench for testing the ASIC in stand-alone simulation is automatically generated eliminating the need for the user to manually generate a test bench.
56
Patent
Memory access debug facility
Andrew Cofler,Isabelle Sename,Bruno Bernard +2 more
- 22 Dec 2000
TL;DR: A computer system includes instruction fetch circuitry for dispatching fetched instructions to a pipelined execution unit, data memory access circuitry and emulator circuitry for use in debug operations.
43
Patent
Target control abstraction for debugging embedded systems
Gregory Hogdal,Yadhu N. Gopalan,David M. Sauntry,James A. Stulz +3 more
- 24 Apr 2000
TL;DR: In this paper, the target control abstraction for debugging embedded systems is presented, where a non-hardware-specific debugging interface is used for communication between a debugger for the embedded system and the hardware of the embedded systems.
37
References
Patent
Method and system for benchmarking computers
John L. Gustafson
- 29 Oct 1990
TL;DR: In this article, the authors present a testing system and method for benchmarking computer systems, which includes a store containing a scalable set of tasks to be performed to produce a solution in everincreasing degrees of resolution as a larger number of the tasks are performed.
39
Patent
Integrated circuit logic functions simulator for selectively connected series of preprogrammed PLA devices using generated sequence of address signals being provided between simulated clock cycles
Thomas Winlow
- 19 Feb 1991
TL;DR: A hardware simulator comprises a plurality of interconnected programmable logic devices (20) which are connected via a data bus (22) and a control bus (24). Address signals on control bus are read by an interconnect logic block associated with each device to selectively link the output latches and input latches of the devices as mentioned in this paper.
36
Patent
Simulation method for modifiable simulation model
Kazuhiko Maeda,Sadao Shimoyashiro +1 more
- 19 Apr 1989
TL;DR: In this paper, a simulation method includes a step of modifying a model in a simulation process, detecting elements influenced by the model modification, and a stage of performing a resimulation process while returning to the earliest one of the influenced elements.
29
Patent
Method and apparatus for determining internal status of a processor using simulation guided by acquired data
James L. Tallman
- 19 Sep 1988
TL;DR: In this paper, the internal state of a processor is determined after the execution of each instruction, and the specification of breakpoints is made for the specification and examination of simulated status of the processor on the occurrence of the breakpoints.
17
Patent
Apparatus and method for modeling parallel processing of instructions using sequential execution hardware
Thomas Basilio Genduso,Shauchi Ong +1 more
- 19 Jun 1990
TL;DR: In this article, a system for modeling computer instruction execution is described, where a combinational logic unit receives multibit data words from the public status register, as well as a source of program code.
17
Related Papers (5)
Stephen A. Stelting,Olav Maassen-Van Leeuwen +1 more
- 08 Feb 2011
Karsten Schulz,Maria E. Orlowska +1 more
- 31 Jul 2003
Karsten Schulz,Maria E. Orlowska +1 more
- 29 Jul 2003
Evren Eryurek,Kadir Kavaklioglu +1 more
- 30 Aug 2001