1. What is the error correction capacity of HVD code?
The Horizontal-Vertical-Diagonal error detecting and correcting code (HVD) uses four direction simple parity bits to detect up to 7 errors or detect up to 4 error bits and correct up to three errors. It was proposed in multiple continuous errors correct coding (MCECC) with an interesting error correction capacity of up to 12 errors. The 104-bit codeword length is generated after duplication. The error correction capacity is lower in techniques not joined with crosstalk avoidance. Combining crosstalk avoidance with EDAC codes increased the error-correcting capacity but also increased the bit overhead and power consumption.
read more
2. What is the mechanism of HVD code encoder and decoder?
The HVD code encoder arranges input data in a matrix and derives four sets of parity check bits: horizontal (H), vertical (V), slash diagonal (D), and backslash diagonal (D'). A parity check bit is added for each set. The encoder algorithm produces a 114-bit codeword. The decoder algorithm uses syndrome of parity check bits to detect or correct errors. If all syndrome bits are zeros, no error or undetectable state. If not, it detects up to 7 errors or corrects up to 3 errors and detects up to 4 errors, depending on the intersection among parity check bits.
read more
3. How are masked parity bits obtained in the given system?
In the given system, masked parity bits are obtained directly for each row. The masked parity bits are encoded from each row using adaptive Hamming code. These parity bits are known as masked parity because they are not added to the codeword nor transmitted. The masked parity bits are derived from the horizontal parity bits. The codeword consists of only data bits, horizontal parity bits, and vertical parity bits, which the sender transmits. Masked parity J bits are obtained using XOR logic operation, where i=3n and n=0,1,2,...,7. The vertical parity bits are obtained by VCj = Jj Jj+12, where j = 0, 1, ...,11. The codeword consists of 52 bits, including 20 parity bits, and is duplicated to become 104 bits before transmission to enhance crosstalk avoidance. The decoder algorithm for this code involves separating the received data into two blocks, calculating the syndrome for each type of parity check bit, comparing the syndrome of horizontal check bits to choose the copy with fewer errors, and determining whether these errors are correct based on the syndrome for both horizontal and vertical check bits.
read more
4. How does the reliability of HVD and CCAEC codes compare?
The reliability analysis results show that the HVD method has higher reliability than CCAEC due to its correction and detection capacity. HVD can correct all messages with two and three errors and 96.7% of total messages with four errors. On the other hand, CCAEC code can correct 98.5%, 92.8%, and 83.6% of all messages with two, three, and four errors, respectively. However, CCAEC code has high power consumption due to its high voltage swing compared to HVD code. Overall, HVD code remains a more reliable and efficient code for handling reliability issues in NoC, and its performance can be improved by implementing a simple crosstalk avoidance method, such as increasing link spacing.
read more