Compact Functional Testing for Neuromorphic Computing Circuits

Question

1. What is the proposed method for generating compact functional test sets for SNN hardware accelerators?

2. AI hardware accelerators testing methods?

3. How do SNNs differ from traditional ANNs?

4. What is the proposed algorithm for SNNs functional test generation?

Accepted Answer

The proposed method for generating compact functional test sets for SNN hardware accelerators involves using available samples from the training and testing sets as functional tests. A fault-agnostic metric is used to assess the fault detection capability of each sample based on how close the sample is to being misclassified. The underlying hypothesis is that such corner samples lying close to the classification hyper-boundary will be classified differently if a fault occurs, thus producing a distinguishing output compared to the nominal fault-free case. Based on this metric, test samples are cumulatively added according to their ranking, and it is demonstrated that compact functional test sets with the size of a few tens of tests can achieve 100% fault coverage of critical faults. A good percentage of benign faults can also be detected, which is beneficial since they are considered as reliability hazards. The proposed method can be used for fast post-manufacturing testing and can also be stored on-chip for periodical online testing in idle times. The method is demonstrated for SNNs at behavioral-level and on actual neuromorphic hardware.

Accepted Answer

AI hardware accelerators testing methods include DfT methods, test generation algorithms, symptom detectors, Selective Triple Modular Redundancy (TMR), algorithmic-based error detection, on-line test methods, behavioral-level fault modeling, fault injection experiments, weight bounding, neuron saturation faults, BIST technique, inherent fault resilience, fault-tolerance schemes, and functional test generation. These methods aim to detect faults, ensure fault tolerance, and improve the reliability of AI hardware accelerators. They are discussed in various research papers, such as [2], [17], [18], [19], [20], [11], [21], [22], [23], [24], [25], [13], [26], [27], [28], [29], [30], [31], [32], [33], [34], [16], [35], [36], [37], [38]. These methods are crucial for developing robust and reliable AI hardware accelerators for applications like SNNs.

Accepted Answer

SNNs differ from traditional ANNs in the way information flows. In SNNs, information flows as spike trains propagating across network layers asynchronously, resembling the biological brain operation. Unlike ANNs, SNNs use the Integrate & Fire (I&F) neuron model, which integrates spikes from incoming synapses and fires a spike when the membrane potential exceeds a threshold. SNNs can also have refractory periods and leakage behavior. The synapse operation in SNNs is similar to biological synapses, where a synapse receives spikes and stimulates the membrane potential of post-synaptic neurons. SNNs are believed to offer faster inference and lower energy consumption compared to ANNs, but training them can be complex. The input type also differs, with SNNs processing continuous-time event flow instead of sequence of static frames.

Accepted Answer

The proposed algorithm for SNNs functional test generation selects tests from the set of available samples in the training and testing sets. It ranks the input samples based on their scores, which are calculated using the firing rate as the classification criterion. The algorithm generates a test set of size T by considering the top T higher-score samples. It evaluates the cumulative fault coverage by sequentially adding the next top-ranked samples and dropping detected faults from the fault list. The algorithm stops adding samples when the fault coverage saturates. The size of the test set needed to reach 100% fault coverage for critical faults is in the order of a few tens of samples. The total number of inferences for test generation and fault coverage evaluation dominates the test generation time. The indicator function and fault coverage indicator are used to measure the detection of faults and the percentage of faults detected by a particular test, respectively. The global fault coverage of a test set is defined as the percentage of faults detected by all tests in the set.

Accepted Answer

The three cognitive tasks performed by convolutional SNNs in V. SNN CASE STUDIES are: 1) Classifying the N-MNIST dataset, 2) Classifying IBM's DVS gesture dataset, and 3) Classifying 4 poker card symbols. These tasks are achieved using three different convolutional SNNs, each trained for a specific task. The winning class is determined based on the most triggered neuron at the output layer. The architectures of these SNNs are shown in Figs. 2, 3, and 4, respectively. CNNs, which are used in these SNNs, consist of convolutional layers with feature maps and subsampling layers. These layers allow synapse reuse and reduce the number of synapses compared to Fully Connected networks. The N-MNIST and IBM's DVS gesture SNNs are designed and simulated in Python, while the poker card-symbols SNN is implemented on an FPGA-based neuromorphic hardware platform.

Accepted Answer

The fundamental building block of poker card-symbols SNN hardware implementation is a generic event-driven configurable convolutional node. This node consists of three main blocks: a convolutional unit with a 128 x 128 I&F neuron array for convolution calculations, an internal configuration block for interpreting the node's configuration data, and a router for event transmission according to a predefined routing scheme. This building block is crucial for processing the poker card symbols dataset and extracting the 32 x 32 pixel window that shows the centered symbol. The SNN design, implemented in VHDL on a Zynq UltraScale+ TM MPSoC ZCU104 FPGA board, utilizes this node to efficiently process and analyze the poker card symbols data.

Accepted Answer

Fault modeling at behavioral-level offers faster test generation and produces actual samples, such as images, that are directly portable to hardware. This approach allows for a more efficient testing process, as it does not require hardware-level implementation. However, it's important to note that the fault coverage obtained may not accurately reflect the true fault coverage of the actual hardware implementation. Despite this limitation, behavioral-level fault modeling remains a valuable method for testing neural networks, as it provides a practical and accessible means of identifying potential faults in the system.

Accepted Answer

Common synapse faults considered in the literature include disabled synapses, stuck-weight synapses, and saturated synapse weights. However, this synapse fault model is not realistic from a hardware perspective since real-weighted synapses after model training in software are quantized and stored as digital words in an on-die memory. A hardware-aware synapse fault model is used, where weight values are quantized, bit-flips are performed across bit positions, and the binary value is mapped back to a real value. This fault model corresponds to synapse weight perturbation, which can be significant if one or more Most Significant Bits (MSBs) are flipped.

Accepted Answer

The main SNN parameters stored in neuromorphic hardware include synapse weights, feature maps size and center-shift, neuron threshold, leakage, refractory period, router parameters, and splitter parameters. Each parameter has an 8-bit integer representation. The hardware is reconfigurable, allowing for on-chip memory storage of these parameters. This enables efficient processing and adaptation of spiking neural networks. The parameters are crucial for the proper functioning and performance of the SNN, as they determine the network's behavior and response to input stimuli. By storing these parameters in on-chip memory, the hardware can quickly access and modify them, leading to faster and more efficient computation. The neuromorphic hardware's ability to reconfigure and store these parameters in on-chip memory makes it suitable for various applications, including pattern recognition, sensory processing, and decision-making tasks. Overall, the storage and management of these parameters play a vital role in the hardware's ability to emulate and simulate the behavior of biological neural networks.

Accepted Answer

Neuron saturation faults are not compensated and can severely perturb the propagating spike trains, leading to a significant impact on network classification accuracy. Dead neuron faults are generally benign except in the last layer, while timing variations are also benign apart from the last layer. Synapse faults, particularly positively saturated weights, can be critical, primarily for synapses connecting the last two layers. However, extreme faults like dead synapses and positively saturated weights are not realistic from a hardware perspective. Using a hardware-aware synapse fault model, such as bit-flips on quantized weights, has a smaller impact on network classification accuracy. Overall, neuron saturation faults are likely to be critical, while many other faults are likely to be benign and can be excluded from fault simulation.

Accepted Answer

A clear trend is observed, i.e., samples with low margin, or equivalently with high score, tend to achieve a higher fault coverage. This means that input samples with relatively large margin values may show small deviation in their fault detection capability, whereas for input samples with small margin values, the deviation can be significant. Additionally, a flat fault coverage curve does not necessarily imply that adding more samples with larger margins to the test set is meaningless, as they may be achieving the same fault coverage but detecting a different set of faults compared to the faults already detected by samples of higher ranking.

Accepted Answer

Synthetic samples generated by DeepXplore and DeepTest algorithms improve ANN classification accuracy by generating error-inducing corner test cases. These test cases are used for retraining the ANN, aiming at maximizing neuron coverage. The goal is to ensure that each neuron has a test that makes it highly active. By representing real-world samples through these synthetic samples, the algorithms enhance the ANN's ability to classify accurately. The generated test cases target improving classification performance rather than hardware-level fault detection. However, it would be interesting to investigate whether these synthetic samples can also achieve high fault coverage.

Accepted Answer

The proposed test generation algorithm consists of two steps. Step (a) involves ranking available input samples based on their fault coverage ability, using inference data from a pre-trained SNN model. This step is independent of the fault model and can be completed quickly. Step (b) requires fault simulation, with the effort proportional to the SNN size. The number of fault locations and functional tests needed increases with SNN size. To reduce fault simulation effort, impactful fault locations are considered. The highest ranked input sample detects a high number of faults, and previous faults are excluded in each step. Step (b) is a one-time effort and can be significant for large SNNs. Once the functional test set is generated, it becomes a fixed test program in high-volume production. A larger dataset size may lead to a more compact functional test set.

Accepted Answer

The Victor-Purpura metric is a distance measure used to quantify the difference between two spike trains. It defines the distance as the minimum cost required to transform one spike train into the other via a path of elementary steps. The cost is inversely proportional to the score of the functional test. There are two kinds of elementary steps: adding or deleting a spike, assigned a cost of 1, and shifting in time the occurrence of a single spike, assigned a cost of q * |t|, where q is a parameter that expresses the relative sensitivity of the metric to precise timing of spikes. By setting q = 0, we recover the spike-count difference metric used in this work. In the limit q = , it is less costly to add or delete spikes than to shift a spike, making the distance between two spike trains the total number of non-synchronous spikes.

Accepted Answer

The proposed method generates compact functional test sets for SNN hardware accelerators by performing inference only once for each sample on the nominal network and recording the output neuron spiking activity. This process is already spent during training. Afterward, fault injection experiments are conducted using the highly ranked samples to compute fault coverage based on a fault model. The results from three SNNs, including one mapped to neuromorphic hardware on an FPGA, demonstrate that the method generates highly compact functional test sets capable of detecting all faults, even those causing the smallest accuracy drop, such as a single sample misclassification.

Compact Functional Testing for Neuromorphic Computing Circuits

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Most frequently asked questions

1. What is the proposed method for generating compact functional test sets for SNN hardware accelerators?

2. AI hardware accelerators testing methods?

3. How do SNNs differ from traditional ANNs?

4. What is the proposed algorithm for SNNs functional test generation?

5. What are the three cognitive tasks performed by convolutional SNNs in V. SNN CASE STUDIES?

6. What is the fundamental building block of poker card-symbols SNN hardware implementation?

7. What are the advantages of fault modeling at behavioral-level?

8. What are common synapse faults considered in the literature?

9. What are the main SNN parameters stored in neuromorphic hardware?

10. What is the impact of neuron saturation faults on network classification accuracy in SNNs?

11. What is the trend observed in fault coverage values as margin values decrease for small margin values and increase for large margin values?

12. How do synthetic samples generated by DeepXplore and DeepTest algorithms improve ANN classification accuracy?

13. What are the steps in the proposed test generation algorithm?

14. What is the Victor-Purpura metric?

15. How does the proposed method generate compact functional test sets for SNN hardware accelerators?

Citations

Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives

Testing and Reliability of Spiking Neural Networks: A Review of the State-of-the-Art

Signature Driven Post-Manufacture Testing and Tuning of RRAM Spiking Neural Networks for Yield Recovery

Low-Complexity Algorithmic Test Generation for Neuromorphic Chips

Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks

References

Gradient-based learning applied to document recognition

Dropout: a simple way to prevent neural networks from overfitting

A million spiking-neuron integrated circuit with a scalable communication network and interface

Loihi: A Neuromorphic Manycore Processor with On-Chip Learning

Analog VLSI and Neural Systems

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