Comments on "A Two's Complement Parallel Array Multiplication Algorithm"

TL;DR: The design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier is presented, which reduces hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system.

TL;DR: This paper describes the design and implementation of a high-speed low-power 16 by 16 two's complement parallel multiplier that uses optimized radix-4 Booth encoders to generate the partial products, and an array of strategically placed (3,2), (5,3), and (7,4) counters to reduce the partial Products to sum and carry vectors.

TL;DR: In this paper, the authors present efficient methods for performing unsigned or two's complement integer multiplication with overflow detection or saturation, which have significantly less area and delay than conventional methods for integer multiplication.

TL;DR: This work proposes to use dedicated hardware accelerators like squaring and cubing units to perform squares and cubes to reduce power consumption per computation by more than 50% and more than 40% using dedicated units, respectively.