Journal Article10.1109/43.391740
Combinational and sequential logic optimization by redundancy addition and removal
Luis Entrena,Kwang-Ting Cheng +1 more
127
TL;DR: This paper presents a method for multilevel logic optimization for combinational and synchronous sequential circuits that can efficiently identify those wires for addition that would create more redundancies elsewhere in the network.
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Abstract: This paper presents a method for multilevel logic optimization for combinational and synchronous sequential circuits. The circuits are optimized through iterative addition and removal of redundancies. Adding redundant wires to a circuit may cause one or many existing irredundant wires and/or gates to become redundant. If the amount of added redundancies is less than the amount of created redundancies, the transformation of adding followed by removing redundancies will result in a smaller circuit. Based upon the Automatic Test Pattern Generation (ATPG) techniques, the proposed method can efficiently identify those wires for addition that would create more redundancies elsewhere in the network. Experiments on ISCAS-85 combinational benchmark circuits show that best results are obtained for most of them. For sequential circuits, experimental results on MCNC FSM benchmarks and ISCAS-89 sequential benchmark circuits show that a significant amount of area reduction can be achieved beyond combinational optimization and sequential redundancy removal. >
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Citations
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FPGA Design Automation: A Survey
Deming Chen,Jason Cong,Peichen Pan +2 more
- 25 Oct 2006
TL;DR: All major steps in FPGA design flow which includes: routing and placement, circuit clustering, technology mapping and architecture-specific optimization, physical synthesis, RT-level and behavior-level synthesis, and power optimization are covered.
Identifying sequential redundancies without search
Mahesh A. Iyer,David E. Long,Miron Abramovici +2 more
- 01 Jun 1996
TL;DR: An efficient algorithm, FIRES, is presented, to identify c-cycle redundancies without search and it is shown that the redundant faults identified by FIRES are not easy targets for state-of-the-art sequential rest generators.
87
A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists
Paul Tafertshofer,Andreas Ganz,Manfred Henftling +2 more
- 13 Nov 1997
TL;DR: A flexible and efficient approach to evaluating implications as well as deriving indirect implications in logic circuits based on a graph model of a circuit's clause description called implication graph which combines both the flexibility of SAT-based techniques and high efficiency of structure based methods.
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation
TL;DR: IGRAINE is proposed, a fast and flexible engine for performing implication, justification, and propagation in combinational circuits that is specifically optimized with respect to these tasks that is easily included into new applications that require ATPG-based methods.
58
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TL;DR: An improved implication procedure and an improved unique sensitization procedure significantly advance the deterministic test pattern generation and redundancy identification especially for those faults, for which it is difficult to generate a test pattern or to prove them to be redundant, respectively.
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TL;DR: Based on the sophisticated strategies used in the automatic test pattern generation system SOCRATES, this article presented several concepts aiming at a further improvement and acceleration of the deterministic test pattern generator and redundancy identification process.
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BOLD: The Boulder Optimal Logic Design system
Gary D. Hachtel,M. Lightner,K. Bartlett,D. Bostwick,R. Jacoby,P. Moceyunas,C.R. Morrison,X. Du,Eric M. Schwarz +8 more
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TL;DR: The BOLD (Boulder-Optimal Logic Design) system is a set of software tools that optimally transform an arbitrary combinational logic description into a standard cell, gate array, or complex CMOS gate technology.
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Multi-level logic optimization by redundancy addition and removal
Kwang-Ting Cheng,Luis Entrena +1 more
- 22 Feb 1993
TL;DR: A multilevel logic optimization technique is presented that is a generalization of redundancy removal and Boolean resubstitution that can efficiently locate redundant wires and/or nodes after adding a redundant wire.
110
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