Journal Article10.1109/TNANO.2009.2036845
CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits
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TL;DR: A novel design technique for ternary logic gates based onCNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs, which provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier.
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Abstract: This paper presents a novel design of ternary logic gates using carbon nanotube (CNT) FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. A resistive-load CNTFET-based ternary logic design has been proposed to implement ternary logic based on CNTFET. In this paper, a novel design technique for ternary logic gates based on CNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs. Especially, the proposed ternary logic gate design technique combined with the conventional binary logic gate design technique provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier. Extensive simulation results using SPICE are reported to show that the proposed ternary logic gates consume significantly lower power and delay than the previous resistive-load CNTFET gates implementations. In realistic circuit application, the utilization of the proposed ternary gates combined with binary gates results in over 90% reductions in terms of the power delay product.
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Citations
Design and Implementation of CNTFET-Based Reversible Combinational Digital Circuits Using the GDI Technique for Ultra-low Power Applications
Maryam Shaveisi,Abbas Rezaei +1 more
TL;DR: This paper attempts to present various CNTFET-based reversible combinational circuits such as multiplexers and decoders by simultaneous use of the reversible Fredkin gate and Gate Diffusion Input (GDI) technique to improve the speed, PDP, and EDP of complex arithmetic structures.
6
Design Of Hardware Efficient High Speed Multiplier Using Modified Ternary Logic
TL;DR: A novel design for a parallel multiplier using ternary logic based on reduced routing and chip area, an alternative to conventional binary logic and a combination of binary and ternARY logic to enjoy the benefits of two is presented.
6
CNFET-Based Ultra-Low-Power Dual- $$V_{DD}$$ V DD Ternary Half Adder
TL;DR: The proposed design utilizes both the available ternary power supply voltages and prevents direct path between the power supplies and ground, thus significantly reducing the power dissipation as compared to the conventional designs.
6
Noise Margin analysis of Efficient CNTFET- based Standard Ternary Inverter
24 Jan 2023
TL;DR: In this paper , the authors proposed a standard ternary inverter and compared noise margin, power consumption, delay, and PDP measurements with existing standard TERNARY inverters, showing that the proposed STI has a 68.6% higher noise margin than the existing designs.
6
Design of a low power three bit ternary prefix adder using CNTFET technology
Jacob Lijitha Merlin,T. E. Ayoob Khan,T. A. Shahul Hameed +2 more
- 16 Apr 2020
TL;DR: In this article, a carry propagate-generate concept is used in order to implement the ternary prefix adder using Carbon Nanotube Field Effect Transistor (CNTFET) technology.
6
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