Journal Article10.1109/TNANO.2009.2036845
CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits
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TL;DR: A novel design technique for ternary logic gates based onCNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs, which provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier.
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Abstract: This paper presents a novel design of ternary logic gates using carbon nanotube (CNT) FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. A resistive-load CNTFET-based ternary logic design has been proposed to implement ternary logic based on CNTFET. In this paper, a novel design technique for ternary logic gates based on CNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs. Especially, the proposed ternary logic gate design technique combined with the conventional binary logic gate design technique provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier. Extensive simulation results using SPICE are reported to show that the proposed ternary logic gates consume significantly lower power and delay than the previous resistive-load CNTFET gates implementations. In realistic circuit application, the utilization of the proposed ternary gates combined with binary gates results in over 90% reductions in terms of the power delay product.
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Citations
Structure and a Detailed Analysis of Various Simulation Results of CNTFET: A Review
Himanshu Gautam,Prateek Bindra +1 more
TL;DR: In this paper, a detailed review on the carbon nanotube Filed Effect Transistors (CNTFETs) has been given, and various simulation results have also been included in order to provide better understanding about the carbon Nanotubes field effect transistors.
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Design of a novel ternary SRAM sense amplifier using CNFET
Liu Zizhao,Tao Pan,Song Jia,Uan Wang +3 more
- 01 Oct 2017
TL;DR: A novel design of a ternary SRAM sense amplifier using carbon nanotube field-effect transistors (CNFETs) is presented, which can achieve 87.5% enhancement in speed, 84.2% and 85.6% in PDP, compared with a terNary DRAMsense amplifier and the ternARY SRAM without sense amplifier.
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CNTFET-based Digital Arithmetic Circuit Designs in Ternary Logic with Improved Performance
Namineni Gireesh,Shaik Javid Basha,Ahmed Elbarbary +2 more
TL;DR: This study proposes CNTFET-based ternary logic circuits, specifically a half-adder and multiplier, achieving 54.44% and 45% transistor count reduction, resulting in 37.01-45.87% delay, power, and energy improvements compared to existing circuits.
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Ternary Competitive to Binary: A Novel Implementation of Ternary Logic Using Depletion-mode and Conventional MOSFETs
Hyundong Lee,Hyeseung Jang,Jihyeong Yun,Huijeen Jin,Jongbeom Na Minsu Han Byeonggwan Kim Younghoon Kim,Yeji Kim,Taigon Song +6 more
- 01 May 2022
TL;DR: A ternary logic system based on depletion-mode MOSfETs and conventional MOSFETs that can truly compete with binary systems in terms of power and delay is proposed.
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Design of content addressable memory cell using carbon nanotube field effect transistors
Subhajit Das,Debaprasad Das,Hafizur Rahaman +2 more
- 01 Sep 2016
TL;DR: In this paper, a low voltage stable SRAM based 11-transistor high speed content addressable memory (CAM) unit using dual gate (DG) Schottky-barrier carbon nanotube field effect transistor (SB-CNTFET) is presented.
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