Journal Article10.1109/TNANO.2009.2036845
CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits
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TL;DR: A novel design technique for ternary logic gates based onCNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs, which provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier.
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Abstract: This paper presents a novel design of ternary logic gates using carbon nanotube (CNT) FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. A resistive-load CNTFET-based ternary logic design has been proposed to implement ternary logic based on CNTFET. In this paper, a novel design technique for ternary logic gates based on CNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs. Especially, the proposed ternary logic gate design technique combined with the conventional binary logic gate design technique provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier. Extensive simulation results using SPICE are reported to show that the proposed ternary logic gates consume significantly lower power and delay than the previous resistive-load CNTFET gates implementations. In realistic circuit application, the utilization of the proposed ternary gates combined with binary gates results in over 90% reductions in terms of the power delay product.
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Citations
A Novel Design Approach for Ternary Compressor Cells Based on CNTFETs
TL;DR: A universal method for designing ternary 3-2 and 4-2 compressor cells based on carbon nanotube field-effect transistors (CNTFETs) is presented and uses unique properties of CNTFets, such as adjustable threshold voltage by changing CNT diameter and ballistic carrier transportation.
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Design of low‐power high‐speed CNFET 1‐trit unbalanced ternary multiplier
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Implementing a Ternary Inverter Using Dual-Pocket Tunnel Field-Effect Transistors
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TL;DR: In this article, a dual pocket tunnel FET (DP-TFET) was proposed for low power applications, which can exhibit ternary inverter voltage transfer characteristics with three stable output voltage levels.
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An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology
TL;DR: In this article , a novel ultra-low power and energy-efficient ternary half-Adder (THA) circuit based on unary operators, two power supplies (dual-VDD), VDD, VDD and VDD/2, and two 3:1 multiplexers in 32 nm GNRFET technology is presented.
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Design and performance evaluation of a low transistor ternary CNTFET SRAM cell
Pramod Srinivasan,Anirudha Shyamprasad Bhat,Sneh Lata Murotiya,Anu Gupta +3 more
- 16 Mar 2015
TL;DR: In this paper, the authors presented a novel design of 10 Transistor ternary memory cell, with separate read and write lines, and extensive HSPICE simulations have validated the read-write functionality of the design.
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