Journal Article10.1109/TNANO.2009.2036845
CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits
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TL;DR: A novel design technique for ternary logic gates based onCNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs, which provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier.
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Abstract: This paper presents a novel design of ternary logic gates using carbon nanotube (CNT) FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. A resistive-load CNTFET-based ternary logic design has been proposed to implement ternary logic based on CNTFET. In this paper, a novel design technique for ternary logic gates based on CNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs. Especially, the proposed ternary logic gate design technique combined with the conventional binary logic gate design technique provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier. Extensive simulation results using SPICE are reported to show that the proposed ternary logic gates consume significantly lower power and delay than the previous resistive-load CNTFET gates implementations. In realistic circuit application, the utilization of the proposed ternary gates combined with binary gates results in over 90% reductions in terms of the power delay product.
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Citations
Novel Ternary Logic Gates Design in Nanoelectronics
TL;DR: Novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is reduced considerably are proposed in which ST-OR and ST-AND are generated directly instead of ST-NAND andST-NOR.
19
Energy efficient design of CNFET-based multi-digit ternary adders
TL;DR: The proposed multi-digit adder uses efficient half-adders to generate Half-Sum and Half-Carry outputs that are used to compute carry-out at each digit-adder stage using a delay optimized carry generator and low-power encoders.
19
DPL-based novel time equalized CMOS ternary-to-binary converter
Aloke Kumar Saha,Dipankar Pal +1 more
TL;DR: Radix-3 (Ternary) logic has been receiving renewed attention as a feasible alternative to conventional Radix-2 system in processor-design and multi-valued logic-design due to computational-ease, sparsity, and robustness as discussed by the authors.
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Highly-Efficient CNTFET-Based Unbalanced Ternary Logic Gates
TL;DR: In this article , the authors used carbon nanotube field-effect transistors (CNTFETs) for the design and implementation of highly efficient ternary logic gates such as the standard ternarary inverter (STI), ternaray buffer (TBUF), terrary OR (TOR), and ternay AND (TAND), which reduced power dissipation and energy consumption by at least 8.55% and 11.38% respectively.
18
Efficient ternary comparator on CMOS technology
TL;DR: A new idea to compare 2-ternary-inputs is proposed using Double-Pass-Transistor-Logic realized on Normal-Process-Enhancement-type-MOS (NPEMOS-technology) without threshold modification.
18
References
Logic circuits with carbon nanotube transistors
TL;DR: This work demonstrates logic circuits with field-effect transistors based on single carbon nanotubes that exhibit a range of digital logic operations, such as an inverter, a logic NOR, a static random-access memory cell, and an ac ring oscillator.
A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region
Jie Deng,Hon-Sum Philip Wong +1 more
TL;DR: In this paper, a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field effect transistors (CNFETs) is presented.
867
Growth of Single-Walled Carbon Nanotubes from Discrete Catalytic Nanoparticles of Various Sizes
TL;DR: In this article, the diameters of single-walled carbon nanotubes are determined by their diameters in the cores of catalytic nanoparticles with diameters between 1−2 nm and 3−5 nm.
859
Theory of ballistic nanotransistors
TL;DR: In this paper, numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors, and the model reduces to Natori's theory of the ballistic MOSFET.