Journal Article10.1145/383251.383256
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
Chris Chu,D. F. Wong +1 more
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TL;DR: This paper considers the delay minimization problem of an interconnect wire by simultaneously considering buffer insertion, buffer sizing and wire sizing and provides elegant closed form optimal solutions for all three problems.
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Abstract: In this paper, we consider the delay minimization problem of an interconnect wire by simultaneously considering buffer insertion, buffer sizing and wire sizing. We consider three cases, namely using no buffer (i.e., wire sizing alone), using a given number of buffers, and using the optimal number of buffers. We provide elegant closed form optimal solutions for all three problems. These closed form solutions are useful in early stages of the VLSI design flow such as logic synthesis and floorplanning.
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Citations
A tutorial on geometric programming
TL;DR: This tutorial paper collects together in one place the basic background material needed to do GP modeling, and shows how to recognize functions and problems compatible with GP, and how to approximate functions or data in a formcompatible with GP.
Fast interconnect synthesis with layer assignment
Zhuo Li,Charles J. Alpert,Shiyan Hu,Tuhin Muhmud,Stephen T. Quay,Paul G. Villarrubia +5 more
- 13 Apr 2008
TL;DR: The importance of layer assignment over wire sizing is outlined, and efficient techniques to perform concurrent buffer insertion and layer assignment to fix the electrical and timing problems, while maintaining speed and efficient use of resources are presented.
43
Geometric programming for circuit optimization
Stephen Boyd,Seung-Jean Kim +1 more
- 03 Apr 2005
TL;DR: This tutorial concerns a method for solving a variety of circuit sizing and optimization problems, which is based on formulating the problem as a geometric program, or a generalized geometric program (GGP).
Accurate estimation of global buffer delay within a floorplan
Charles J. Alpert,Jiang Hu,Sachin S. Sapatnekar,Chin Ngai Sze +3 more
- 07 Nov 2004
TL;DR: The theory of Otten (1998) is extended to show how one can model the blocks into a simple delay estimation technique that applies both to two-pin and to multi-pin nets, and shows remarkable accuracy in predicting delay when compared to an optimal realizable buffer insertion solution.
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
Lizheng Zhang,Yu Hen Hu,Chungping Chen Charlie +2 more
- 07 Jun 2004
TL;DR: A novel statistical timing analysis approach has been developed to analyze the behavior of two important pipelined architectures for multiple clock-cycle global interconnect, namely, the flip-flop inserted global wire and the latch insertedglobal wire using Monte Carlo simulation.
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CMOS Circuit Speed and Buffer Optimization
N. Hedenstierna,Kjell Jeppson +1 more
TL;DR: An improved timing model for CMOS combinational logic is presented, which yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform.
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Optimal wire sizing and buffer insertion for low power and a generalized delay model
TL;DR: This approach represents the first work on buffer insertion to incorporate signal slew into the delay model while guaranteeing optimality and efficiently computes the complete, optimal power-delay trade-off curve for added design flexibility.
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Wire segmenting for improved buffer insertion
Charles J. Alpert,Anirudh Devgan +1 more
- 13 Jun 1997
TL;DR: Weshow that using wire segmenting as a precursor to buffer insertion produces solutions within a few percent of optimal, while using only seconds of CPU time is shown.
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