Proceedings Article10.1145/267665.267712
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Chris Chu,D. F. Wong +1 more
- 01 Apr 1997
- pp 192-197
TL;DR: This paper considers the delay minimization problem of an interconnect wire by simultaneously considering buffer insertion, buffer sizing and wire sizing and provides elegant closed form optimal solutions for all three problems.
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Abstract: In this paper, we consider the delay minimization problem of an interconnect wire by simultaneously considering buffer insertion, buffer sizing and wire sizing. We consider three cases, namely using no buffer (i.e., wire sizing alone), using a given number of buffers, and using the optimal number of buffers. We provide elegant closed form optimal solutions for all three problems. These closed form solutions are useful in early stages of the VLSI design flow such as logic synthesis and floorplanning.
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Citations
•Book
On-Chip Communication Architectures: System on Chip Interconnect
Sudeep Pasricha,Nikil Dutt +1 more
- 01 Jan 2008
TL;DR: This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design, and will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on- chip communication architectures.
267
Buffer block planning for interconnect-driven floorplanning
Jason Cong,Tianming Kong,David Z. Pan +2 more
- 07 Nov 1999
TL;DR: An effective buffer block planning (BBP) algorithm is developed to perform buffer clustering such that the overall chip area and the buffer block number can be minimized.
Buffer insertion for noise and delay optimization
Charles J. Alpert,Anirudh Devgan,Stephen T. Quay +2 more
- 01 May 1998
TL;DR: This work presents comprehensive buffer insertion techniques for noise and delay optimisation, and shows that the performance penalty induced by optimizing both delay and noise as opposed to only delay is 2%.
165
Buffer insertion with accurate gate and interconnect delay computation
Charles J. Alpert,Anirudh Devgan,Stephen T. Quay +2 more
- 01 Jun 1999
TL;DR: This work proposes to integrate accurate wire and gate delay models into Van Ginneken's buffer insertion algorithm (1990) via the propagation of moments and driving point admittances up the routing tree and verified the effectiveness of this approach on an industry design.
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Optimal wire sizing and buffer insertion for low power and a generalized delay model
TL;DR: This approach represents the first work on buffer insertion to incorporate signal slew into the delay model while guaranteeing optimality and efficiently computes the complete, optimal power-delay trade-off curve for added design flexibility.
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Wire segmenting for improved buffer insertion
Charles J. Alpert,Anirudh Devgan +1 more
- 13 Jun 1997
TL;DR: Weshow that using wire segmenting as a precursor to buffer insertion produces solutions within a few percent of optimal, while using only seconds of CPU time is shown.
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