Clock synchronizing logical device

TL;DR: In this paper, the phase of an input binary signal to a clock with resolution smaller than the clock period was detected and the result was processed by a phase detection circuit 25, where the phase was detected at four regions having a resolution shorter than clock period.

Abstract: PURPOSE:To obtain a clock synchronizing logical device with a small delay error of output by detecting the phase of an input binary signal to a clock with resolution smaller than the clock period and processing the result. CONSTITUTION:The input binary signal from a terminal 11 is inputted to an FF11 of the clock synchronizing logical circuit 24 and also to delay lines 17- 19 of a phase detection circuit 25. The synchronism of the clock signal from a terminal 12 is taken as 4ns, for example, 1-3ns delay is given respectively to the delay lines 17-19 and their output is inputted respectively to FFs 21-23. Thus, the circuit 25 detects the phase of the input signal ot the clock at four regions having a resolution smaller than the clock period. An output of the circuit 25 is encoded (26) and its output is decoded (42) via delay lines 31, 32 slightly shorter the delay time of FFs 13-FF1n of the circuit 24 and FFs 28, 29 and inputted to a detection circuit 49. The circuit 49 ANDs the decode output with the output signal of the FF1n, selects one of the binary signals of different phases es and outputs via a correction delay circuit 51 and an OR gate 37.