Patent
Clock distribution network
Mario J. Paniccia,Ian A. Young,Thomas P. Thomas,Valluri R. Rao +3 more
- 26 Jun 1998
154
TL;DR: In this paper, an optical source is configured to emit optical pulses at a desired clock frequency and the optical pulses are separated into a plurality of split optical pulses, each of which is received by a clock receiver node in a semiconductor die.
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Abstract: A method and an apparatus for providing an optical clock distribution network. In one embodiment, an optical source is configured to emit optical pulses at a desired clock frequency. The optical pulses are separated into a plurality of split optical pulses, each of which is received by a clock receiver node in a semiconductor die. In one embodiment, each clock receiver node locally generates a photocurrent in response to the split optical beams. Each of the photocurrents is locally converted into voltage and thus into local clock signals, which are used to clock the local area of the integrated circuit. In one embodiment, the semiconductor die includes an additional clock receiver node used to clock a clock generation circuit included in the semiconductor die. The clock generation circuit generates clock signals that are in phase with each other and the other clock signals generated throughout the semiconductor die. In one embodiment, the clock signals generated by the clock generation circuit are used to clock and phase lock input/output communications on the semiconductor die as well as off chip input/output communications between the semiconductor die and other external semiconductor dice of the system.
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Citations
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Progress in the methodologies for the electrical modeling of interconnects and electronic packages
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TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
185
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Patent
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Seungug Koh,H.W. Carter,Joseph T. Boyd +2 more
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TL;DR: In this article, an optical waveguide H-tree design is provided for global clock distribution on multichip modules (MCM) which has nearly zero clock skew and is useful for a distributed computer system environment.
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Patent
Method and means for optical detection of charge density modulation in a semiconductor
Harley K. Heinrich,David M. Bloom +1 more
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