Book Chapter10.1007/978-3-030-96415-3_3
Chip Planning
01 Jan 2022
- pp 53-93
About: The article was published on 01 Jan 2022. The article focuses on the topics: Floorplan & Block (permutation group theory).
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References
Optimization by Simulated Annealing
TL;DR: There is a deep and useful connection between statistical mechanics and multivariate or combinatorial optimization (finding the minimum of a given function depending on many parameters), and a detailed analogy with annealing in solids provides a framework for optimization of very large and complex systems.
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Handbook of Algorithms for Physical Design Automation
Charles J. Alpert,Dinesh P. Mehta,Sachin S. Sapatnekar +2 more
- 12 Nov 2008
TL;DR: Handbook of Algorithms for Physical Design Automation provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade.
Modern floorplanning based on B/sup */-tree and fast simulated annealing
Tung-Chieh Chen,Yao-Wen Chang +1 more
TL;DR: This floorplanner uses B/sup */-tree floorplan representation based on fast three-stage simulated annealing (SA) scheme called Fast-SA and obtains much smaller dead space for the floorplanning with hard/soft macro blocks, compared with the most recent work.
Efficient Floorplan Area Optimization
D. F. Wong,P. S. Sakhamuri +1 more
- 01 Jun 1989
TL;DR: An algorithm for general hierarchical floorplan area optimization that combines the curve-adding technique used in the case of slicing floorplans and a new technique that computes shape curves by iterative modification of the shape and dimensions of individual modules is presented.
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DeFer: deferred decision making enabled fixed-outline floorplanner
Jackey Z. Yan,Chris Chu +1 more
- 08 Jun 2008
TL;DR: DeFer is a fast, high-quality and non-stochastic fixed-outline floorplanning algorithm that achieves the best success rate, the best wirelength and the best runtime on average compared with other state-of-the-art floorplanners.
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