Patent
Cell placement method for microelectronic integrated circuit combining clustering, cluster placement and de-clustering
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TL;DR: In this paper, a large number of microelectronic circuit cells are first grouped into disjoint clusters by an optimization-driven clustering technique, which uses both local and global connectivity information among the cells.
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Abstract: A large number of microelectronic circuit cells that are interconnected by a set of wiring nets are optimally placed on an integrated circuit chip such that all interconnects can be routed and the total wirelength of the interconnects is minimized. Cells are first grouped into disjoint clusters by an optimization-driven clustering technique, which uses both local and global connectivity information among the cells. This technique uses Rent's rule for combining pairs of neighboring clusters, and selects among pairs of clusters having the same Rent's exponent using distance information derived from global optimization processing. Clusters are prevented from growing to an excessive size by limiting the number of cells per cluster and the maximum area per cluster to predetermined maximum values. After the clusters are generated, they are placed using an optimization-driven placement technique, preferably "Gordian". Finally, the cells within each cluster are de-clustered and locally placed using a partitioning technique, preferably "min-cut".
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Citations
Patent
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TL;DR: In this paper, a method for design optimization using logical and physical information is provided, which includes a behavioral description of an integrated circuit or a portion of an Integrated Circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements.
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TL;DR: In this article, a system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is described, where each cell may be part of a cell net containing multiple cells.
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Placement method for integrated circuit design using topo-clustering
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Patent
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- 17 Apr 1998
TL;DR: In this paper, the authors proposed a method and apparatus to partition high fanout nets into smaller subnets, which includes the steps of identifying elementary pairs of pins in the net, each such elementary pair defining a line; eliminating lines such that a planar graph is formed; eliminating further lines such as a spanning tree is formed, connecting each pin in net; identifying basic elements, each basic element forming a portion of said spanning tree; and constructing a connected cover for said net, said connected cover comprising a plurality of said basic elements.
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