Cell Broadband Engine Debugging for Unknown Events

TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.

TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.

TL;DR: This paper presents accelerated algorithms for restoring circuit state elements from the traces collected during a debug session, by exploiting bitwise parallelism and introduces new metrics that guide the automated selection of trace signals, which can enhance the real-time observability during in-system debug.

TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.

TL;DR: The implementation of an 1149.1 compliant test controller for a low cost, high performance CMOS RISC processor is described and includes features to support I/sub DDQ/ test, internal test, a hardware assisted instruction buffer test, and at speed internal state capture.

TL;DR: The design choices that were made and the considerations that led to those choices are explored, and the architectures and methodologies used to implement the design choices are presented.

TL;DR: Some of the innovative debug features included in the CELL processor design that were critical for efficient bring-up in a limited access environment are explained.

TL;DR: With a focus on a short time to volume production, the UltraSparc microprocessor design incorporated innovative features that optimize test, debug and manufacture.