Open Access
Cache performance analysis of algorithms
James D. Fix,Richard E. Ladner +1 more
- 01 Jan 2002
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TL;DR: The cache performance analysis of algorithms whose primary goal is to determine the number of cache hits and cache misses that an algorithm incurs is developed, view an algorithm as a combination of basic memory access patterns, analyze each pattern's cache performance, and apply the analysis to accurately predict the cache performance of the algorithm.
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Abstract: How effectively a program uses the memory hierarchy of a computer system can have a tremendous impact on its performance. The failure of a program to access data in the cache memory, hence the need to access that data in main memory, has a cost of up to 100 cycles on today's systems, a penalty that is expected to rise with future systems. As a result much recent algorithm design research has been conscious of the cache, and has focused on its effective use. Understanding the behavior of the cache when developing algorithms is crucial to such research.
We develop the cache performance analysis of algorithms whose primary goal is to determine the number of cache hits and cache misses that an algorithm incurs. We view an algorithm as a combination of basic memory access patterns, analyze each pattern's cache performance, and apply the analysis to accurately predict the cache performance of the algorithm. Our analysis is precise: we pay attention to constant factors and quantify performance for even moderate data sizes. Our caching model is realistic: we determine the performance of our access pattern models for direct-mapped caches and caches with a limited degree of set-associativity. For certain patterns that arise in accessing common data structures, we demonstrate and prove that set-associativity yields little or no benefit over direct-mapped caching.
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Citations
•Posted Content
Towards a Theory of Cache-Efficient Algorithms
TL;DR: A model that enables the running time of an algorithm on a computer with a memory hierarchy with limited associativity, in terms of various cache parameters is presented, and cache-efficient algorithms in the single-level cache model are obtained.
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Scanning and Traversing: Maintaining Data for Traversals in a Memory Hierarchy
Michael A. Bender,Richard Cole,Erik D. Demaine,Martin Farach-Colton,Martin Farach-Colton +4 more
- 17 Sep 2002
TL;DR: This work explores the problem of maintaining a dynamic ordered set subject to insertions, deletions, and traversals of k consecutive elements on more realistic memory models: the cache-oblivious model, which applies to unknown and multi-level memory hierarchies, and sequential-access models, where sequential block transfers are less expensive than random block transfers.
Worst-Case Efficient External-Memory Priority Queues
Gerth Stølting Brodal,Jyrki Katajainen +1 more
- 01 Jan 1998
TL;DR: In this paper, the authors present a data structure that handles any intermixed sequence of Insert and DeleteMin operations such that in every disjoint interval of B consecutive priorityqueue operations at most clogM/B N/M I/Os are performed, for some positive constant c. The best earlier solutions can only handle a sequence of S operations with O(σ i=1 S 1/B log M/B Ni/M) I/O, where N i denotes the number of elements stored in the data structure prior to the ith operation, without
35
Analysis of scratch-pad and data-cache performance using statistical methods
Javed Absar,Francky Catthoor +1 more
- 24 Jan 2006
TL;DR: It is proved that the scratch-pad, with an optimal mapping, has always outperform the cache and how to map dynamic applications efficiently to scratch-pads or cache is demonstrated.
•Journal Article
Erratum: An Analytic Study of Caching in Computer Systems.
Duane Buck,Mukesh Singhal +1 more
TL;DR: In this paper, the independent reference model (IRM) of data reference in conjunction with the least recently used (LRU) cache block replacement policy is analyzed for the cache performance.
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