Cache memory for set associative system

TL;DR: In this article, the read/write control is applied to a way address memory, 1st and 2nd higher level address memory means, and a data memory means respectively based on the output results of two higher-level address comparison means.

Abstract: PURPOSE:To extremely increase the number of ways in a simple circuit constitution by applying the read/write control to a way address memory means, 1st and 2nd higher level address memory means, and a data memory means respectively based on the output results of two higher level address comparison means. CONSTITUTION:When a higher level address is fixed, a way address memory means 9 outputs the way address corresponding to said fixed address. When this way address and a lower level address are fixed, a 2nd higher level address memory means 11 outputs the higher address values corresponding to said way address and lower level address. A 2nd comparison means 13 compares the higher level address outputted from the means 11 with a higher level address given from a CPU. When the coincidence (hit) is obtained between both addresses, the corresponding data on a data memory means 14 receives an access and is sent to the CPU. Thus, it is possible to extremely increase the number of ways in the same circuit constitution as a conventional set associative system.