Patent
Cache memory apparatus, cache control method, and microprocessor system
Takashi Kitahara
- 02 Nov 2012
4
TL;DR: In this article, the authors present a cache memory that caches an instruction code corresponding to a fetch address and a cache control circuit that controls the instruction code to be cached in the cache memory.
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Abstract: A cache memory apparatus according to the present invention includes a cache memory that caches an instruction code corresponding to a fetch address and a cache control circuit that controls the instruction code to be cached in the cache memory. The cache control circuit caches an instruction code corresponding to a subroutine when the fetch address indicates a branch into the subroutine and disables the instruction code to be cached when the number of the instruction codes to be cached exceeds a previously set maximum number.
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Citations
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Disabling a command associated with a memory device
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TL;DR: In this article, a memory device may contain device processing logic and a mode register, a register that may specify a mode of operation of the memory device, and a field in the mode register may hold a value that may indicate whether a command associated with the memory devices is disabled.
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Mélanie Emanuelle Lucie Teyssier,Philippe Pierre Maurice Luc,Albin Pierick Tonnerre +2 more
- 21 Dec 2012
TL;DR: In this paper, a load store pipeline includes an issue queue and load store circuitry 24, which includes the plurality of access slot circuits 26 to 40 and dependency tracking circuitry 42, 44, 46, 48.
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Tai-Yuan Tseng,Hiroyuki Mizukoshi,Chi-Lin Hsu,Yan Li +3 more
- 08 Jun 2018
TL;DR: In this article, a first processor generates first control signals to control a first circuit to perform memory operations on memory cells, and a second number of second physical signal lines delivers converted control signals.
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Fingerprint recognition system of cabinet
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TL;DR: In this article, a fingerprint recognition system of a cabinet is described, which consists of a fingerprint lock control module and a mechanical lock structure module, where the fingerprint recognition module is electrically connected with the control module, and the mechanical lock module is installed on a cabinet unit of the cabinet.
References
Patent
Storage control system and storage control method
Jun Matsuda,Mikio Fukuoka,Keishi Tamura +2 more
- 16 Dec 2005
TL;DR: In this paper, a storage control system that can prevent capacity in a cache memory from being overloaded even when the access performance of a controller in a storage controller to an external storage device in a external storage controller is permanently or temporarily poor is discussed.
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Patent
Data processor with branch target address cache and subroutine return address cache and method of operation
Ralph Mcgarity
- 23 Sep 1996
TL;DR: In this article, a branch and link address cache ( ++ BLAC ++ ) and a Branch Target Address Cache (BTAC) are used for storing a number of recently encountered fetch address-target address pairs.
43
Patent
Multilevel instruction cache
Chi-Hung Chi
- 08 Apr 1994
TL;DR: In this article, a cache memory for use between a processing unit and a main memory includes a prefetch buffer, a use buffer, and a head buffer, which prefetches instructions from contiguous memory locations after the address specified by the program counter.
31
Patent
Cache system and cache memory control device controlling cache memory having two access modes
Teruyuki Itoh,Naoto Okumura +1 more
- 02 Jul 2003
TL;DR: A branch/prefetch judgement portion, in receipt of a branch request signal, sets a cache access mode switch signal to an “H” level as mentioned in this paper, thus, a cache memory operates in the 1-cycle access mode consuming a large amount of power.
21
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