Patent
Cache Controller Device, Interfacing Method and Programming Method Using the Same
Hwang Soo Lee,Jung-Keum Kim,Il Song Han,Young Serk Shim +3 more
- 04 Jan 2010
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TL;DR: In this article, a cache controller device prefetching and supplying data distributed in a memory to a main processor is described, and an interfacing method and a programming method using the same.
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Abstract: Disclosed are a cache controller device, an interfacing method and a programming method using the same. The cache controller device prefetching and supplying data distributed in a memory to a main processor, includes: a cache temporarily storing data in a memory block having a limited size; a cache controller circularly reading out the data from the memory block to a cache memory, or transferring the data from the cache memory to the cache; and a memory input/output controller controlling prefetching the data to the cache, or transferring the data from the cache to a memory.
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Citations
Patent
Techniques for evaluating query predicates during in-memory table scans
Dinesh Das,Jiaqi Yan,Mohamed Zait,Nirav Vyas +3 more
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TL;DR: In this paper, the authors describe techniques for filtering data from a table during an in-memory scan to avoid scanning unnecessary columnar units and reduce the overhead of decompressing, row stitching and distributing data during evaluation.
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Patent
Use Of Dynamic Dictionary Encoding With An Associated Hash Table To Support Many-To-Many Joins And Aggregations
Adam Kociubes,Ekrem Soylemez,Hyemin Chung +2 more
- 22 Jul 2015
TL;DR: In this paper, the authors describe techniques for using a dynamic dictionary encoding with an associated hash table to support many-to-many join and aggregation operations, where the hash table is a hash bucket for each join key that corresponds to an instance of a flag value.
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Efficient hardware instructions for single instruction multiple data processors: fast fixed-length value compression
Shasank K. Chavan,Phumpong Watanaprakornkul,Victor Chen +2 more
- 15 Jul 2016
TL;DR: In this paper, methods and apparatuses for determining setmembership using Single Instruction Multiple Data (SIMD) architecture are presented. But they do not address the problem of determining set-membership in a stream of variable-length values.
16
Patent
Methods and systems for fast set-membership tests using one or more processors that support single instruction multiple data instructions
Shasank K. Chavan,Phumpong Watanaprakornkul +1 more
- 22 Jul 2014
TL;DR: In this paper, methods and apparatuses for determining set-membership using SIMD architecture are presented, in parallel, for determining whether multiple values in a first set of values are members of a second set of value.
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Patent
Requesting memory spaces and resources using a memory controller
Edgar R. Cordero,Varkey K. Varghese,Diyanesh B. Chinnakkonda Vidyapoornachary +2 more
- 23 Jul 2013
TL;DR: In this paper, a memory controller may be configured to communicate the request from the first resource to a computer program, and use the resource in response to an indication from the computer program that the resource is available.
14
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