Bus interface unit

TL;DR: In this paper, a frame check sequence tester is used to check the correctness of the parity of the parallel data and the output of the tester can be altered if the parity is incorrect.

Abstract: A bus interface unit for interfacing a serial bit data bus to a parallel bit data handling system includes a receiver for acquiring serial data from the bus. A clock generates a clock signal at a frequency corresponding to frequency of bits in the serial data. A clock processor receives the serial data and the clock signal to generate a clock processor signal for processing the serial data. A serial to parallel converter responsive to the serial data and the clock processor signal converts the serial data to parallel bit data. An output driver provides the parallel bit data to the parallel bit data handling system. A frame check sequence tester responsive to the serial data and the clock signal provides a validity output signal when the frame check sequence is recognized by the tester. The tester includes a plurality of devices operating in parallel to increase speed. A serial to parallel converter converts data received from the parallel bit data handling device to serial form data. The parity of the parallel data is checked. A frame check sequence generator of essentially the same configuration as the tester provides a word based on the content of the data which is altered if the parity is incorrect. A transmitter places the serial form data and the frame check sequence word on the data bus.