Bus arbitration system

Patent

Bus arbitration system

- 04 Jun 1990

3

TL;DR: In this paper, the authors rationalize the arbitration of bus using right by changing bus acquisition priority in accordance with data volume stored at present in a first in first out (FIFO) storage device.

Abstract: PURPOSE:To rationalize the arbitration of bus using right by changing bus acquisition priority in accordance with data volume stored at present in a first in first out (FIFO) storage device to apply the bus using right. CONSTITUTION:When three bus masters compete with each other and the bus master 1 (21) with the highest priority frequently requests the bus and occupies it, the bus master 3 (23) can not process the output data of an I/O device 4, so that unprocessed data are stored in the FIFO 3. When the number of data stored in the FIFO 3 exceeds a certain fixed value (stored volume generating the probability of data loss), a data storage state signal LS is turned to '1' and the bus priority is changed. Thereby, the bus master 3 (23) can process the data of the I/O device 4 without losing it.

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Citations

Patent

Bus arbitration between an I/O device and processor for memory access using FIFO buffer with queue holding bus access flag bit

Hirofumi Sudo

- 08 Dec 1995

TL;DR: In this article, the bus arbitration circuit determines the bus available right so as to grant a priority right for data write-in processing by the input/output device rather than data write in processing by a processing device when the bus arbitrator receives the flag signal.

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1

Patent

System zum dynamischen Ändern der Ablaufpriorität eines Empfangsfifos

Darren Abramson, +1 more

- 01 Feb 1999

TL;DR: In this article, the authors discuss the dynamischen Andern der¯¯¯¯Entleerungsprioritat and the dynamical change in the dynamics of andern.

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1

Patent

Bus adjustment method and bus adjustment device

Kinoshita Yuji, +1 more

- 28 Sep 2006

TL;DR: In this article, a bus adjustment circuit is proposed to adjust bus use requests issued from a plurality of bus masters to reflect the importance of individual data transfer, and a priority determination circuit determines a bus master which requests the access to a data block having the highest priority on the basis of the output from the data transfer access priority setting table circuit 48, and permits the use of the bus to this bus master.

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