Bridging modularity and optimality: delay-insensitive interfacing in asynchronous circuits synthesis

TL;DR: The approach allows logic synthesis to proceed independently for all the locally SI blocks and yields functionally correct circuits without requiring any synthesis/layout iteration or interaction, which simplifies dramatically the timing convergence problem for ASICs.

Abstract: Two trends are of major concern for digital circuit designers: the relative increase of interconnect delays with respect to gate delays and the demand for design reuse. Both pose difficult problems to synchronous design styles, and can be tackled more naturally within the asynchronous paradigm. Unfortunately even in asynchronous design the normal hypotheses about the delays of gates and wires are often overly optimistic. One of the popular assumptions is to consider gate delays to be arbitrary while neglecting the skew in wire delays (so-called speed-independence (SI) assumption). Taking wire delays into account is possible and in its extreme leads to delay-insensitive (DI) implementations which work correctly under any wire delay distribution. However, such implementations are costly. This work suggests to separate all on-chip interconnections into two classes: local (for which the delays can be under control) and global (with arbitrary delays). This leads to locally SI globally DI implementations which are more practical than fully DI circuits and are in better correspondence with technology parameters than fully SI circuits. Our approach allows logic synthesis to proceed independently for all the locally SI blocks and yields functionally correct circuits without requiring any synthesis/layout iteration or interaction. This simplifies dramatically the timing convergence problem for ASICs. We tackle the problem at the behavior level and develop a simple transformation which ensures delay-insensitive properties for particular wires. The method is illustrated by a realistic design example. The preliminary experimental results show that the area and performance penalty are within 40% and 20%, respectively.