Bounding worst-case data cache behavior by analytically deriving cache reference patterns
Harini Ramaprasad,Frank Mueller +1 more
- 07 Mar 2005
- pp 148-157
TL;DR: This work exploits the power of the cache miss equations (CME) framework but lifts a number of limitations of traditional CME to generalize the analysis to more arbitrary programs, and devised a transformation, coined "forced" loop fusion, which facilitates the analysis across sequential loops.
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Abstract: While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and particularly data caches) limit the timing predictability for data accesses that may reside in memory or in cache. This is a significant problem for real-time systems. The objective our work is to provide accurate predictions of data cache behavior of scalar and nonscalar references whose reference patterns are known at compile time. Such knowledge about cache behavior provides the basis for significant improvements in bounding the worst-case execution time (WCET) of real-time programs, particularly for hard-to-analyze data caches. We exploit the power of the cache miss equations (CME) framework but lift a number of limitations of traditional CME to generalize the analysis to more arbitrary programs. We further devised a transformation, coined "forced" loop fusion, which facilitates the analysis across sequential loops. Our contributions result in exact data cache reference patterns minus; in contrast to approximate cache miss behavior of prior work. Experimental results indicate improvements on the accuracy of worst-case data cache behavior up to two orders of magnitude over the original approach. In fact, our results closely bound and sometimes even exactly match those obtained by trace-driven simulation for worst-case inputs. The resulting WCET bounds of timing analysis confirm these findings in terms of providing tight bounds. Overall, our contributions lift analytical approaches to predict data cache behavior to a level suitable for efficient static timing analysis and, subsequently, real-time schedulability of tasks with predictable WCET.
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Citations
The worst-case execution-time problem—overview of methods and survey of tools
Reinhard Wilhelm,Jakob Engblom,Andreas Ermedahl,Niklas Holsti,Stephan Thesing,David Whalley,Guillem Bernat,Christian Ferdinand,Reinhold Heckmann,Tulika Mitra,Frank Mueller,Isabelle Puaut,Peter Puschner,Jan Staschulat,Per Stenström +14 more
TL;DR: Different approaches to the determination of upper bounds on execution times are described and several commercially available tools1 and research prototypes are surveyed.
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
TL;DR: The proposed approach can reasonably estimate the worst- case shared L2 instruction cache misses by considering inter-thread instruction conflicts and the WCET of applications running on multi-core processors estimated by the approach is much better than the estimation by simply assuming all L2 instructions are misses.
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
Damien Hardy,Isabelle Puaut +1 more
- 30 Nov 2008
TL;DR: This paper proposes a safe static instruction cache analysis method for multi-level non-inclusive caches, and shows that in all cases WCET estimations are much tighter when considering the cache hierarchy than when considering only the L1 cache.
Scope-Aware Data Cache Analysis for WCET Estimation
Bach Khoa Huynh,Lei Ju,Abhik Roychoudhury +2 more
- 11 Apr 2011
TL;DR: A refined persistence analysis method is presented which fixes the potential underestimation problem in the original persistence analysis and a framework to combine access pattern analysis and abstract interpretation for accurate data cache analysis is proposed.
Real-time and embedded technology and applications symposium (RTAS '05)
Oleg Sokolsky,Tarek Abdelzaher +1 more
TL;DR: RTAS ’05 is the eleventh in the series of annual meetings devoted to the integration of academic and industrial perspectives on theory and practive of real-time and embedded systems and was held in San Francisco, California, on March 7-10.
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