Boron out-diffused surface strap process

TL;DR: The preferred embodiment of the present invention overcome the limitations of the prior art by providing a method for forming the source/drain diffusions in a vertical transistor structure that results in improved channel length uniformity as discussed by the authors.

TL;DR: In this article, an impurity-doped first conductive region is etched back to a first level within the trench and an amorphous silicon layer is then recrystallized.

TL;DR: In this article, a memory cell having a low storage node resistance and a method of manufacturing the same are provided. And a trench type memory cell, in addition to storage node polysilicon, has other conductive material embedded in the storage node.

TL;DR: In this article, a method for controlling isolation layer thickness in deep trenches for semiconductor memories in accordance with the present invention includes the steps of providing a deep trench having a storage node formed therein, the storage node having a buried strap, depositing an isolation layer on the buried strap for providing electrical isolation for the storage nodes, forming a masking layer on isolation layer to mask a portion of the isolation layer in contact with the buried straps, and removing isolation layer except the portion masked by the mask layer such that control of a thickness of the isolator is improved.

TL;DR: In this paper, a silicide bridge is constructed by selectively growing over exposed silicon regions under conditions that provide controlled lateral growth over the thin dielectric without also permitting lateral growth on other insulator regions.

TL;DR: In this paper, a method of simultaneously producing doped silicon filled trenches in areas where a substrate contact is to be produced and trench isolation in other areas was proposed, where Borosilicate glass lines the sidewalls of those trenches where a contact is desired and undoped epitaxially grown silicon filled all the trenches.

TL;DR: In this article, a layer of titanium is evaporated at a temperature of approximately 370° C, so that the titanium has a substantially columnar grain structure and a minimum of matrix material, and bottom portions of the columnar grains have a lateral length that approximates the lateral length of the dielectric separating the source diffusion from the poly-filled trench.

TL;DR: In this paper, a planarizing photoresist is deposited and etched in conjunction with the oxide to the upper surface of the gate electrode, followed by a polycrystalline silicon layer for recrystallization to an upper FET device.