Binary coded decimal to binary conversion

TL;DR: In this paper, a CPU data path portion having an ALU, an adjuster unit, a shifter unit and a shift register unit is disclosed, where the CPU is capable of selectively forming the sum or difference of a first binary to BCD operand and a second BCD to binary operand by arithmetically combining the operands with the ALU to form binary results.

TL;DR: In this paper, an address data converter for converting binary row address information and binary column address information corresponding to data character display locations of a CRT display device having a row/column display field to binary absolute address information is presented.

TL;DR: In this article, a binary-to-binary-coded-decimal (BCD) converter is described, where the binary number is held in a first register and is shifted bit by bit into a second register as the number is converted.

TL;DR: In this paper, successive sum bits produced by the adder are returned, in serial fashion, to the register means and represent a new binary number equal to the digits inserted, to that point, of the decimal number.