Binary addition and multiplication device

Patent

Binary addition and multiplication device

- 21 Sep 1988

4

TL;DR: Binary adders with fixed operand were introduced in this paper, where an adder consisting of at least one cell possessing an input for first binary digits or bits (Ai), an output for second bits (Bi), a backward-carry input (Ri-1), and a forward-carry signal under multiplexed logic were used to add a first bit of arbitrary binary value to a second bit of fixed, known binary value.

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Citations

Patent

Arithmetical unit including accumulating operation

Shinichi Uramoto, +1 more

- 27 Jan 1993

TL;DR: An improved M-bit accumulator for increasing speed and reducing circuit size is presented in this paper, which includes an N-bit (N < M) adder, a first latch having an input coupled to the output of the adder and an output coupled to an input of an adder for latching output when a first clock signal is asserted, an (M-N) bit incrementer, and a clock generating circuit for asserting the second clock signal in synchronism with the first signal only when a carry signal is generated by the adders.

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43

Patent

Neural processor, saturation unit, calculation unit and adder circuit

Vladimir Mikhailovich Chernikov, +4 more

- 31 Dec 1998

TL;DR: In this paper, the authors present a neural processor that includes six registers, a shift register, a AND gate, two FIFOs, a switch, a multiplexer, two saturation units, a calculation unit and a adder circuit to execute operations over vectors of programmable word length data.

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13

Patent

Neuroprocessor, device for calculating saturation functions, calculation device and adder

Vladimir Mikhailovich Chernikov, +4 more

- 31 Dec 1998

TL;DR: In this paper, the authors present a neuroprocessor for the field of calculation techniques and may be used for the emulation of neural networks as well as for the digital processing of signals.

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3

Patent

Unite arithmetique ayant une operation d'accumulation.

Schinichi Uramoto

- 06 Aug 1993

TL;DR: In this article, a unified arithmetique for an operation d'accumulation comprends des premiers moyens d'enregistrement (2a) for enregistrer le resultat d'une operation predetermines d'ordre inferieur d'un additionneur.

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References

Patent

Multifunction full adder

R Pryor

- 21 Jan 1972

TL;DR: In this paper, a pair of exclusive OR gates connected in series are used to produce a binary arithmetic unit which can be used in any binary computational circuit, including a two-way transmission gate switch.

...read moreread less

38

Patent

Binary adder having a fixed operand, and a parallel/serial multiplier comprising such an adder

Francis Jutand, +2 more

- 16 Sep 1987

TL;DR: In this article, a parallel serial binary adder with a fixed operand and a non-fixed operand is presented, which is applied on the control input of a multiplexer.

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