Beyond-Binary Arithmetic: Algorithms and VLSI Implementations.
Takafumi Aoki,Tatsuo Higuchi +1 more
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TL;DR: This paper presents prominent examples of beyond-binary arithmetic algorithms, including a high-radix redundant division algorithm without using lookup tables, and redundant complex arithmetic algorithms for fast real/complex-mixed computations.
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Abstract: Beyond-binary arithmetic algorithms are defined as a new class of computer arithmetic algorithms which employ non-binary data representations to achieve higher performances beyond those of conventional binary algorithms. This paper presents prominent examples of beyond-binary arithmetic algorithms: examples include (i) a high-radix redundant division algorithm without using lookup tables, (ii) a high-radix redundant CORDIC algorithm for fast vector rotation, and (iii) redundant complex arithmetic algorithms for fast real/complex-mixed computations.
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Citations
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Evolutionary synthesis of arithmetic circuit structures
Takafumi Aoki,Naofumi Homma,Tatsuo Higuchi +2 more
- 01 Jan 2004
TL;DR: The Evolutionary Graph Generation (EGG) as discussed by the authors is a graph-based optimization technique for arithmetic circuit synthesis that employs a graphbased representation of individuals and can manipulate the graph structures directly by evolutionary operations.
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Evolutionary Synthesis of Arithmetic Circuit Structures
TL;DR: This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to arithmetic circuit synthesis.
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Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams
Naofumi Homma,Katsuhiko Degawa,Takafumi Aoki,Tatsuo Higuchi +3 more
- 13 May 2007
TL;DR: The potential of the CTD- based method is demonstrated through an experimental design of the Redundant-Binary (RB) adder in multiple-valued current-mode logic that achieves about 32-57% higher performance in terms of power-delay product compared with the conventional designs.
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Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic
Naofumi Homma,Takafumi Aoki,Tatsuo Higuchi +2 more
- 17 May 2006
TL;DR: This paper introduces an extension of CTDs for representing possible fast addition algorithms with redundant number systems and can classify the conventional fast adder structures including those using emerging multiple-valued logic devices into three types in a systematic way.
4
High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language
Y. Watanabe,Naofumi Homma,Katsuhiko Degawa,Takafumi Aoki,Tatsuo Higuchi +4 more
- 22 May 2008
TL;DR: This paper presents a specific cell library containing a multiple-valued signed-digit adder and its related circuits with a 0.35mum CMOS technology, and demonstrates that the proposed method can synthesize a 32times 32-bit parallel multiplier in multiple- valued current-mode logic from an ARITH description.