Proceedings Article10.1145/1065579.1065680
BDD representation for incompletely specified multiple-output logic functions and its applications to functional decomposition
Tsutomu Sasao,Munehiro Matsuura +1 more
- 13 Jun 2005
- pp 373-378
TL;DR: This method is useful for decomposition of incompletely specified multiple-output functions and also useful for the synthesis of LUT cascades in three-valued logic simulation.
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Abstract: A multiple-output function can be represented by a binary decision diagram for characteristic function (BDD/spl I.bar/for/spl I.bar/CF). This paper presents a new method to represent multiple-output incompletely specified functions using BDD/spl I.bar/for/spl I.bar/CF. An algorithm to reduce the widths of BDD/spl I.bar/for/spl I.bar/CFs is presented. This method is useful for decomposition of incompletely specified multiple-output functions. Experimental results for radix converters, adders and a multiplier show that this method is useful for the synthesis of LUT cascades. This data structure is also useful to three-valued logic simulation.
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Citations
On the decomposition of switching functions
Sze-Tsen Hu
- 01 Jun 1961
TL;DR: In this article, the Ashenhurst chart method is generalized to non-junctive decompositions by means of the don't care conditions, which leads to designs of more economical switching circuits to realize the given switching function.
348
•Journal Article
A Method to Decompose Multiple-Output Logic Functions
Tsutomu Sasao,Munehiro Matsuura +1 more
TL;DR: In this article, a method to decompose a given multiple-output circuit into two circuits with intermediate outputs is presented, where a BDD for characteristic function (BDD for CF) is used to represent a multiple-input-multiple-output function.
43
Design Methods for Multiple-Valued Input Address Generators
Tsutomu Sasao
- 17 May 2006
TL;DR: Methods to realize multiple-valued input address generators by multi-level networks of p-input q-output memories by showing a method to simplify the address generators using an auxiliary memory.
Implementation of Multiple-Valued CAM Functions by LUT Cascades
Tsutomu Sasao,Jon T. Butler +1 more
- 17 May 2006
TL;DR: This paper defines multiple-valued CAM functions represented by ordinary CAMs, and shows an approach to realize each CAM function by an LUT cascade, which is a series connection of RAMs.
Radix converters: complexity and implementation by LUT cascades
Tsutomu Sasao
- 19 May 2005
TL;DR: This paper derives several upper bounds on the column multiplicities of decomposition charts that represent radix converters that can be used to estimate the size of LUT cascades to realize radix Converters.
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TL;DR: A theory for (disjunctive and nondisjunctive) function decomposition using the BDD representation of Boolean functions and a novel algorithm for generating the set of all bound variables that make the function decomposable is presented.
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