Asynchronous design by conversion: converting synchronous circuits into asynchronous ones
Alex Branover,Rakefet Kol,Ran Ginosar +2 more
- 16 Feb 2004
- Vol. 2, pp 20870
TL;DR: A novel methodology and algorithm for the design of large low-power asynchronous systems are described, which can adapt its effective operating frequency to the supply voltage, facilitating flexible and efficient power management.
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Abstract: A novel methodology and algorithm for the design of large low-power asynchronous systems are described. The system is synthesized by a commercial tool as a synchronous circuit, and subsequently converted into an asynchronous one. The conversion algorithm consists of extracting input and output sets, replacing the storage elements, identifying fork and join sets, and constructing request and acknowledge networks. A DLAP (doubly latched asynchronous pipeline) architecture is employed. The resulting asynchronous circuit can adapt its effective operating frequency to the supply voltage, facilitating flexible and efficient power management. The algorithm has been validated on several circuits.
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References
Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
TL;DR: The combination of supply scaling and self-timed circuitry which has some unique advantages, and the thorough analysis of the power savings that are possible using this technique are described.
Asynchronous circuits for low power: a DCC error corrector
TL;DR: The authors describe a complete low-power digital compact cassette error corrector using Tangram, a high-level programming language, and designed two asynchronous circuits that correct errors on DCC specifications.
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Automatic synthesis of 3D asynchronous state machines
TL;DR: In this paper, an automatic synthesis tool for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental mode operation, is described, and an algorithm for constructing a three-dimensional next-state table, a heuristic for encoding states, and a procedure for generating necessary constraints for exact logic minimization are presented.
62
A doubly-latched asynchronous pipeline
Rakefet Kol,Ran Ginosar +1 more
- 12 Oct 1997
TL;DR: DLAP, an asynchronous pipeline with master-slave (dual) registers, offers improved performance and is most suitable for converting synchronous circuits into asynchronous ones.
40
A design framework for asynchronous/synchronous circuits based on CHP to HDL translation
M. Renaudin,P. Vivet,F. Robin +2 more
- 19 Apr 1999
TL;DR: An open design framework, which allows mixing asynchronous and synchronous circuit styles, is presented, based on the development of a tool called "CHP/sub 2/VHDL" which automatically translates CSP-like specifications into VHDL programs.
38
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