Patent
Asynchronous data processing system
Joseph Furlong Robert
- 31 Dec 1962
7
About: The article was published on 31 Dec 1962. The article focuses on the topics: Synchronizer & Proactor pattern.
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Citations
Patent
Buffer system for input/output portion of digital data processing system
William F. Bruckert,Barry Flahive,James V. Lacy +2 more
- 31 Oct 1984
TL;DR: In this paper, a data transfer system for use in transferring data between a memory and an input/output system in a digital data processing system is presented, which includes a plurality of buffers into which data can be loaded from either the memory or the input-output system, and a buffer control selects the buffer to be loaded, and control signals from the memory govern the transfer of data from the data into and out of the selected buffer.
65
Patent
Channel data buffer apparatus for a digital data processing system
James T. Moyer
- 25 Jul 1977
TL;DR: In this paper, the data buffer is comprised of eight column-forming byte-wide multirow storage arrays each having its own address mechanism for accessing any desired row therein, and corresponding rows in the different storage arrays provide the corresponding eight-byte rows for the whole data buffer as a whole.
44
Patent
Apparatus for selectively addressing sections and locations in a device controller's memory
Douglas L. Riikonen
- 22 Dec 1975
TL;DR: In this paper, a memory in a device controller is divided into sections which are equal in number to the potential number of devices controllable by the controller, each section having a plurality of storage locations for storing the same topology of information in like positioned locations in the other sections.
36
Patent
System and method for accessing data between a host bus and system memory buses in which each system memory bus has a data path which is twice the width of the data path for the host bus
Marilyn J Lang,Sridhar Begur,Robert Campbell,Carol E Bassett +3 more
- 24 Dec 1992
TL;DR: In this article, a microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode, using a system memory controller capable of performing the addressing of the memory.
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