Asynchronous Circuit Design

TL;DR: In this article, the authors present a practical guide to asynchronous design with a focus on practical techniques and real-world applications, as well as a large variety of design styles, while the emphasis throughout is on practical technique and real world applications.

TL;DR: Synchronous and asynchronous elastic circuits can be designed, analyzed, and optimized using similar techniques, and choices between synchronous and asynchronous implementations are localized and deferred until late in the design process.

TL;DR: The aims of Part I of this book are to introduce readers with background in synchronous digital circuit design to the fundamentals of asynchronous circuit design such that they are able to read and understand the literature, and to provide readers with an understanding of the “nature” of asynchronous circuits such as they are to design non-trivial circuits with interesting performance parameters.

TL;DR: A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in different clock domains is presented.

TL;DR: In this article, the authors present a practical guide to asynchronous design with a focus on practical techniques and real-world applications, as well as a large variety of design styles, while the emphasis throughout is on practical technique and real world applications.

TL;DR: Synchronous and asynchronous elastic circuits can be designed, analyzed, and optimized using similar techniques, and choices between synchronous and asynchronous implementations are localized and deferred until late in the design process.

TL;DR: The aims of Part I of this book are to introduce readers with background in synchronous digital circuit design to the fundamentals of asynchronous circuit design such that they are able to read and understand the literature, and to provide readers with an understanding of the “nature” of asynchronous circuits such as they are to design non-trivial circuits with interesting performance parameters.

TL;DR: A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in different clock domains is presented.