Patent
Asymmetric semiconductor memory device having electrically floating body transistor
Yuniarto Widjaja
- 26 Sep 2011
32
TL;DR: In this paper, an asymmetric, bi-stable semiconductor memory cell is described that includes a floating body region configured to be charged to a level indicative of a state of the memory cell.
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Abstract: Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.
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Citations
Patent
Managing the write performance of an asymmetric memory system
Vijay Karamcheti,Ashish Singhai,Shibabrata Mondal,Ajith Kumar +3 more
- 26 Jun 2013
TL;DR: In this paper, the authors propose a method of managing a hosted NVRAM-based storage subsystem that includes NVRM devices, where the write requests are categorized into subgroups of write requests, where write requests within respective subgroups are mutually exclusive.
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Patent
Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and method of operating
Yuniarto Widjaja
- 07 Feb 2011
TL;DR: In this paper, a semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell, a first region in electrical contact with the floating body, a second region in contact with said floating body and spaced apart from the first region, and a gate positioned between the first and second regions.
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Patent
Method of maintaining the state of semiconductor memory having electrically floating body transistor
Yuniarto Widjaja,Zvi Or-Bach +1 more
- 16 Apr 2015
TL;DR: In this article, a back bias is applied to the memory cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cells.
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Patent
Semiconductor memory having both volatile and non-volatile functionality and method of operating
Yuniarto Widjaja
- 29 Oct 2010
TL;DR: In this paper, a semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory and non-volatile memory.
55
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Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
Yuniarto Widjaja
- 26 May 2011
TL;DR: In this article, a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a nonvolatile memory comprising a resistance change element configured to stores data stored in the floating body under any one of a plurality of predetermined conditions.
42
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