Patent
Array multiplier operating in one's complement format
William L. Borgerding,Vithal R. Patel +1 more
- 10 Mar 1981
17
TL;DR: In this article, the authors present a method and apparatus for performing a two's complement, single or double precision digital multiply, whereby the multiplication is performed in a one's complement format in a gate array assembly and then converted to a two-position format.
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Abstract: A method and apparatus for performing a two's complement, single or double precision digital multiply, whereby the multiplication is performed in a one's complement format in a gate array assembly and then converted to a two's complement format. The gate array assembly generally multiplying successive eight bit bytes of the multiplier two bits at a time in each of four ranks to the full width multiplicand and producing a partial sum and carry at the end of each cycle. Each partial sum and carry then being fedback, aligned and added into the partial sum and carry produced during the multiplication of the next successive multiplier byte, until the multiplication is complete and at which time the final partial carry is converted and added to the final partial product to produce the final product.
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Citations
Patent
Two-pass multiplier/accumulator circuit
George P. Chamberlin
- 01 Jul 1983
TL;DR: In this paper, a two-pass multiplier/accumulator circuit is presented, which performs various arithmetic operations on operands contained within an X Register 10 and a Y Register 20 and places the result in an Accumulator Register 40.
68
Patent
Asynchronous high speed processor having high speed memories with domino circuits contained therein
Michael J. Cochran
- 11 Apr 1984
TL;DR: In this article, the minimum possible delay time is implemented through the providing a completion pulse upon the completion of each operation and initiating a subsequent operation at the receipt of the completion pulse.
40
Patent
Circuit and method for accumulating partial products of a single, double or mixed precision multiplication
Marvin A. Denman,John M. Young,Mitch Kirkpatrick Alsup +2 more
- 15 Apr 1988
TL;DR: In this article, a circuit for use in conjunction with a multiplier receives completed product bits and a portion of sum and carry bits which, when accumulated, provide a complete output product operand.
29
Patent
Digital multiplier architecture with triple array summation of partial products
James Yuan Wei,Hedayati Khosrow +1 more
- 31 Aug 1987
TL;DR: In this article, a modified Booth algorithm was proposed to minimize the number of partial products generated by the two adder arrays in order to optimize the speed of the circuit, where the partial products are divided between the two arrays in a manner which optimizes the speed.
24
Patent
Digital multiplication circuit for use in a microprocessor
Daniel L. Essig,Luat Q. Pham,Joe F. Sexton,Graham S. Tubbs +3 more
- 03 Oct 1983
TL;DR: In this article, a digital multiplication circuit for a microprocessor utilizes a modified Booth algorithm for implementing the digital multiplication of two numbers and includes a Booth recoder for recoding the multiplier into a selected number, n, of Booth operation sets where n is a positive integer that equals one-half the number of bits in the multiplier.
22
References
Patent
High speed combinatorial digital multiplier
Robert C. Ghest,Hua-Thye Chua,John M. Birkner +2 more
- 18 Aug 1977
TL;DR: In this paper, a high speed 8 by 8 digital multiplier was proposed for implementation on a single semiconductor chip including an encoder for implementing the Modified Booth Algorithm to encode the eight multiplier digits.
55
Patent
High speed multiplier using carry-save/propagate pipeline with sparse carries
Robert Clement Letteney,Samuel Robert Levine,David Tjeng-Ming Shen,Arnold Weinberger +3 more
- 04 May 1979
TL;DR: In this article, a high speed multiply apparatus minimizes latch requirements and I/O pin requirement between chips by a new configuration which iteratively adds four multiples of a multiplicand in a stage of 4-2 carry save adders which then feed four-bit parallel adders each having four sum outputs and a carry output from the highest order bit position.
34
Patent
Binary two's complement multiplier processing two multiplier bits per cycle
Leonard G. Trubisky,Jerry L. Kindell +1 more
- 26 Apr 1972
TL;DR: In this paper, a series of partial product formation cycles are described, where each cycle, a pair of the n multiplier bits is processed, right to left, on the basis of each bit pair configuration and the next multiplier bit, the accumulated partial product is shifted 2 bits right and a selected multiple of the multiplicand is added to or subtracted from the partial product accumulator register.
16
Patent
Binary multiplication by addition with non-verlapping multiplier recording
L Topham,G Amdahl,M Clements +2 more
- 30 Oct 1972
TL;DR: In this paper, the authors present a multiplier method and apparatus for use in a data processing system, where the multiplication is carried out in the form (Ai) (b)+ C(i-1) R1 (i),R2(i) where Ai is one byte of a multiplier operand A, B is a multiplicand, and R 1 (i) and R 2 (i)-1) are partial results obtained in a previous step.
9
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