Journal Article10.1109/PROC.1987.13882
Array architectures for iterative algorithms
H.V. Jagadish,S.K. Rao,Thomas Kailath +2 more
- 01 Sep 1987
- Vol. 75, Iss: 9, pp 1304-1321
80
TL;DR: Regular mesh-connected arrays are shown to be isomorphic to a class of so-called regular iterative algorithms, which include arrays for Fourier Transform, Matrix Multiplication, and Sorting.
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Abstract: Regular mesh-connected arrays are shown to be isomorphic to a class of so-called regular iterative algorithms. For a wide variety of problems it is shown how to obtain appropriate iterative algorithms and then how to translate these algorithms into arrays in a systematic fashion. Several "systolic" arrays presented in the literature are shown to be specific cases of the variety of architectures that can be derived by the techniques presented here. These include arrays for Fourier Transform, Matrix Multiplication, and Sorting.
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Citations
Synthesis of control circuits in folded pipelined DSP architectures
TL;DR: The authors derive conditions for the validity of a specified folding set, and present approaches to generate the dedicated architecture using systematic folding of tasks to operators using the technique used to derive the control circuitry of the hardware architecture.
212
Algorithm transformation techniques for concurrent processors
Keshab K. Parhi
- 01 Dec 1989
TL;DR: Four independent algorithm transformation methodologies-program unfolding, retiming, look-ahead algorithms, and index mapping transformations-are reviewed, which exploit the available parallelism in iterative data-flow programs and create additional parallelism if necessary.
204
Synthesizing systolic arrays with control signals from recurrence equations
TL;DR: A technique for synthesizing systolic arrays which have non-uniform data flow governed by control signals is presented and it is shown how to derive the control signals in such arrays by applying similar pipelining transformations to theselinear conditional expressions.
97
Partitioning techniques for large-grained parallelism
Rakesh Agrawal,H.V. Jagadish +1 more
TL;DR: A model is presented for parallel processing in loosely coupled multiprocessing environments, such as networks of computer workstations, that are amenable to large-grained parallelism that takes into account the overhead involved in data communication to and from a remote processor and can be used to partition a large class of computations optimally.
82
Synthesizing systolic arrays from recurrence equations
Sanjay Rajopadhye,Richard M. Fujimoto +1 more
- 01 Jun 1990
TL;DR: It is shown that merely determining appropriate timing and allocation functions is not enough to guarantee that the architecture is systolic, so the class of Affine Recurrence Equations (AREs) which are a superset of UREs are proposed which enable us to derive syStolic arrays from the ARE.
82
References
Why systolic architectures
TL;DR: The basic principle of systolic architectures is reviewed and it is explained why they should result in cost-effective, highperformance special-purpose systems for a wide range of problems.
Regular iterative algorithms and their implementation on processor arrays
S.K. Rao,Thomas Kailath +1 more
- 01 Mar 1988
TL;DR: Regular iterative algorithms contain all algorithms executed by systolic arrays as a proper subclass and are therefore of considerable importance in real-time signal processing applications.
435
On the design of algorithms for VLSI systolic arrays
D.I. Moldovan
- 01 Jan 1983
TL;DR: This paper is concerned with the mapping of cyclic loop algorithms into special-purpose VLSI arrays and the mapping procedure is based on the mathematical transformations of index sets and data dependence vectors.
417
On supercomputing with systolic/wavefront array processors
Sun-Yuan Kung
- 01 Jan 1984
TL;DR: A wavefront-oriented programming language, which describes the (parallel) data flow in systolic/wavefront-type arrays, is presented and the structural property of parallel recursive algorithms points to the feasibility of a Hierarchical Iterative Flow-Graph Design of VLSI Array Processors.
366
•Book Chapter
Let's Design Algorithms for VLSI Systems
H. T. Kung
- 01 Jan 1979
TL;DR: Examples of algorithms that are suitable for VLSI implementation are given, a taxonomy for algorithms based on their communication structures is provided, and some of the insights that are beginning to emerge from efforts in designing algorithms for V LSI systems are discussed.
296
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