Journal Article10.1109/tc.2022.3191966
ARETE: Accurate Error Assessment via Machine Learning-Guided Dynamic-Timing Analysis
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TL;DR: ARETE as discussed by the authors is a cross-layer fault-injection framework that combines dynamic-binary instrumentation with machine learning-guided dynamic-timing analysis to estimate the location of the injecting errors via dynamic-time analysis.
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Abstract: Nanometer circuits are increasingly prone to timing errors, escalating the need for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fault injection</i> frameworks to accurately evaluate their impact on applications. In this paper, we propose ARETE, a novel cross-layer, fault-injection framework that combines dynamic-binary instrumentation with machine learning-guided dynamic-timing analysis. ARETE enables accurate fault-injection into any application by estimating the location of the injecting errors via dynamic-timing analysis. To accelerate fault-injection, we develop a novel, data-aware, machine learning-based mechanism that dynamically pre-selects the error-prone instructions and limits the application of the costly dynamic-timing analysis only to them. To evaluate ARETE's accuracy, our fully automated toolflow is configured to support fault-injection based on detailed post-layout gate-level simulations as well as via existing workload-agnostic error models. Our results for various workloads, including an autonomous-driving library, show that the location and time of injected errors performed by ARETE, is 89.9% consistent with fault-injection based on full gate-level simulation. On average, ARETE executes 84.6× faster than gate-level simulation and at a cost of 3.4% loss in the program output quality estimation. When compared to the existing statistical fault-injection tools that are based on workload-agnostic error models, ARETE improves the accuracy of fault-injection rate and output quality estimation by 143.9% and 40.4% on average, respectively.
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Citations
Microarchitecture-Aware Timing Error Prediction via Deep Neural Networks
Styliani Tompazi,Georgios Karakonstantis +1 more
- 03 Jul 2023
TL;DR: Microarchitecture-aware timing error prediction via deep neural networks accurately predicts timing errors in nanometer circuits considering microarchitecture and workload parameters. The novel framework combines post-layout dynamic timing analysis and genetic algorithms to generate error-prone microarchitecture-aware samples. NN models are trained and evaluated on these samples, achieving high accuracy and improved scalability.
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ePredictNet: Low Cost Error Prediction Neural Network
Georgios Chatzitsompanis,Georgios Karakonstantis +1 more
- 05 Aug 2024
A Compressed and Accurate Sparse Deep Learning-based Workload-Aware Timing Error Model
Styliani Tompazi,Georgios Karakonstantis +1 more
TL;DR: This study shows that DL can help increase the accuracy and true positive rate (TPR) of workload-aware models for a pipelined floating-point core compared to existing models and demonstrates that removing up to 40% of the total neurons has minimal impact on the accuracy and overall predictive performance of the DL-based timing error models.
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