Proceedings Article10.1109/RSP.2011.5929977
Applying graphics processor acceleration in a software defined radio prototyping environment
William Plishker,George Zaki,Shuvra S. Bhattacharyya,Charles Clancy,John Kuykendall +4 more
- 24 May 2011
- pp 67-73
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TL;DR: A new design flow is proposed that augments a popular existing SDR development environment (GNU Radio), with a dataflow foundation and a stand-alone GPU accelerated library, that gives an SDR developer the ability to prototype a GPU accelerated application and explore its design space fast and effectively.
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Abstract: With higher bandwidth requirements and more complex protocols, software defined radio (SDR) has ever growing computational demands. SDR applications have different levels of parallelism that can be exploited on multicore platforms, but design and programming difficulties have inhibited the adoption of specialized multicore platforms like graphics processors (GPUs). In this work we propose a new design flow that augments a popular existing SDR development environment (GNU Radio), with a dataflow foundation and a stand-alone GPU accelerated library. The approach gives an SDR developer the ability to prototype a GPU accelerated application and explore its design space fast and effectively. We demonstrate this design flow on a standard SDR benchmark and show that deciding how to utilize a GPU can be non-trivial for even relatively simple applications.
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Citations
Towards A Large-Scale Cognitive Radio Network Testbed: Spectrum Sensing, System Architecture, and Distributed Sensing
TL;DR: A comprehensive review of the cognitive radio network testbed built at TTU and goals to use random matrix theory to model the collect data and apply the new models in the context of quantum information are presented.
A fully parallel truncated Viterbi decoder for Software Defined Radio on GPUs
Rongchun Li,Yong Dou,Yu Li,Shi Wang +3 more
- 07 Apr 2013
TL;DR: A map-reduce strategy based on the three-point Viterbi decoding algorithm (TVDA) due to the high parallelization potential is exploited and achieves a performance improvement of 1.2x-3.6x times that of the existing GPU-based implementation of Software-Defined Radio on the Graphics Processing Unit (GPU) platform.
18
Integration of Dataflow-Based Heterogeneous Multiprocessor Scheduling Techniques in GNU Radio
George Zaki,William Plishker,Shuvra S. Bhattacharyya,Charles Clancy,John Kuykendall +4 more
- 01 Feb 2013
TL;DR: This work augments a popular SDR framework with a library that seamlessly allows offloading of algorithm kernels mapped to the GPU without changing the original protocol description, and shows how to utilize Single Instruction Multiple Data units provided in Graphics Processing Units (GPUs) along with vector accelerators implemented in General Purpose Processors (GPPs).
17
Integration of GPU Computing in a Software Radio Environment
Pierre-Henri Horrein,Christine Hennebert,Frédéric Pétrot +2 more
- 01 Oct 2012
TL;DR: This article studies the integration of Graphics Processing Units in a Software Defined Radio environment and proposes a fine grain parallelism solution, which is an extension of the existing solutions but adapted to operations of large computational complexity.
13
Accelerating fast Fourier Transform for wideband channelization
Carlo C. del Mundo,Vignesh Adhinarayanan,Wu-chun Feng +2 more
- 09 Jun 2013
TL;DR: This work considers three generations of AMD GPUs and provides insight into the optimization of FFT on these platforms and outperforms a multithreaded Intel Sandy Bridge CPU with vector extensions by factors of 4.3, 4.9, and 6.6.
References
Synchronous data flow
Edward A. Lee,David G. Messerschmitt +1 more
- 01 Sep 1987
TL;DR: A preliminary SDF software system for automatically generating assembly language code for DSP microcomputers is described, and two new efficiency techniques are introduced, static buffering and an extension to SDF to efficiently implement conditionals.
2K
A GPGPU compiler for memory optimization and parallelism management
Yi Yang,Ping Xiang,Jingfei Kong,Huiyang Zhou +3 more
- 05 Jun 2010
TL;DR: This paper presents a novel optimizing compiler for general purpose computation on graphics processing units (GPGPU), which addresses two major challenges of developing high performance GPGPU programs: effective utilization of GPU memory hierarchy and judicious management of parallelism.
Synthesis of Embedded Software from Synchronous Dataflow Specifications
Shuvra S. Bhattacharyya,Praveen K. Murthy,Edward A. Lee +2 more
- 01 Jun 1999
TL;DR: This paper reviews a set of algorithms for compiling dataflow programs for embedded DSP applications into efficient implementations on programmable digital signal processors that focus primarily on the minimization of code size, and the minimizing of the memory required for the buffers that implement the communication channels in the input dataflow graph.
Multiprocessor resource allocation for throughput-constrained synchronous dataflow graphs
Sander Stuijk,Twan Basten,Marc Geilen,Henk Corporaal +3 more
- 04 Jun 2007
TL;DR: A new resource allocation strategy which works directly on SDFGs is presented, building on an efficient technique to calculate throughput of a bound and scheduled SDFG, and experimental results show that the strategy is effective in terms of run-time and allocated resources.
198
Hardware/software partitioning using integer programming
Ralf Niemann,Peter Marwedel +1 more
- 11 Mar 1996
TL;DR: The paper shows that using integer programming to solve the hardware/software partitioning problem is feasible and leads to promising results.